PHY registers can not be accessed through MDIO interface of C6678

What is more, infact all memory space of Ethernet Subsystem can not be accessed rightly both in our boards and on the C6678 EVM.

Need your quick reply.

Thank you very much.

Sounds like the LPSC (clocking domain) is turned off for Ethernet / SGMII - Check MDSTAT8 register (0x0235 0820)  This will be 0x3 if it's enabled and 0x0 if it's disabled.

Best Regards,

Chad

Thank you Chad for your quickly reply.

Picture below is what we get in address 0x02350820  of C6678:

Clock domain has already been turned on.

Picture below is what we get in the memory space  from  0x02000000  of C6678:

All zeros after the address of 0x02000080.

Picture below is what we get in address 0x02000380  of C6678,which is the USERACCESS register. 

It can not been changed to any other value except 0. Each time we change the value of  register address  0x02000380 ,

the value of register address  0x0200040C  will be changed to a new value (the old value plus one).

Can you please help to explain and solve the problem?

 Thank you very much.

Hi all,

we have a very similar problem. We have a c6678 (TMX) connected to a 5461 phy on SGMII link 1. The phy establishes a GBit link after some time when connecting to a switch, but it seems that the SGMII connection to the DSP does not come up. So I wanted to check the MDIO registers to see if the settings are appropriate, but I cannot find a way to access the MDO registers inside the phy.

I have tried to use the CSL functions of the 6678. There are two functions for MDIO register communication, CSL_MDIO_getUserAccessRegister() and CSL_MDIO_setUserAccessRegister(). As far as I understand the implementations in csl_mdioAux.h,

(1) CSL_MDIO_setUserAccessRegister() provides only write access to the MDIO registers, since the write bit of the USERACCESS register is set, and

(2) CSL_MDIO_getUserAccessRegister() does not provide *any* access to the MDIO regs since the GO bit is not set, the function simply returns the content of the USERACCESS register.

Maybe I do not understand the MDIO mechanism correctly, but It seems to me, that CSL does not provide functions for read access to the MDIO registers. However, when I call the CSL_MDIO_isPhyLinked(), I get a correct link status of the phy, so I think that the MDIO interface seems functional in our design.

So I have the same question as Jason: How to access MDIO registers? Our memory dumps show the same behavior as described by Jason. I did not try the EVM, however.

Regards, Marcus

The platform library uses the CSL MDIO set user access. Check the C6678_phy.c and the platform.c file for how the PHY is set and accessed using MDIO (platform_phy_link_status function in platform.c).

thanks,

Arun.

Thanks Arun,

but in C6678_phy.c I cannot see any call to CSL MDIO functions, and in platform_phy_link_status function in platform.c does only a write access.
IMHO, there is no CSL function to *read* MDIO registers. However, after some experiments, I could read and write the MDIO registers in the following way (Note that our phy is wired to phy address 1):


#include <ti/csl/csl_mdio.h>
#include <ti/csl/csl_mdioAux.h>



void testMDIOAccess ()
{
     CSL_MDIO_USERACCESS  userAccReg;

     /* Setup MDIO Interface */
     CSL_MDIO_enablePreamble();
     CSL_MDIO_setClkDivVal(200);
     CSL_MDIO_enableStateMachine();

     /* print some status */
     printf ("StateMachineEnabled() : %d\n", CSL_MDIO_isStateMachineEnabled());
     printf ("StateMachineIdle() : %d\n", CSL_MDIO_isStateMachineIdle());
     printf ("PhyAlive(1) : %d\n",CSL_MDIO_isPhyAlive(1));
     printf ("PhyLinked(1) : %d\n",CSL_MDIO_isPhyLinked(1));
     printf ("HighestUserChannel() : %d\n",CSL_MDIO_getHighestUserChannel());


     /* ***** Read register 9 ********** */
     userAccReg.phyAddr = 1;       // Setup phy and MDIO register address
     userAccReg.regAddr = 9;

     // Do a read access to the phy's MDIO register
     hMdioRegs->USER_GROUP [0].USER_ACCESS_REG   =   CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, userAccReg.phyAddr) |
                                                     CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, userAccReg.regAddr) |
                                                     CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 0) |
                                                     CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u);

     // Wait for MDIO state machine finishing
     while (CSL_MDIO_isUserAccessPending (0));

     // Read result from USERACCESS register
     CSL_MDIO_getUserAccessRegister (0, &userAccReg);

     printf ("MDIO register 0x09 is 0x%04x\n", userAccReg.data);


     /* ***** Write register 9 ********** */

     userAccReg.data = 0x1b00; // Setup phy and MDIO register address and data
     userAccReg.phyAddr = 1;
     userAccReg.regAddr = 9;
     userAccReg.go = 1;

     /* Do a write access to the phy's MDI register using CSL function */
     CSL_MDIO_setUserAccessRegister (0, &userAccReg);

     // Wait for MDIO state machine finishing
     while (CSL_MDIO_isUserAccessPending (0));


     /* ***** Again read register 9 ********** */

     userAccReg.phyAddr = 1;       // Setup phy and MDIO register address
     userAccReg.regAddr = 9;

     userAccReg.data = 0;            // Clear data field before read access to be sure to get current MDIO data

     // Do a read access to the phy's MDIO register
     hMdioRegs->USER_GROUP [0].USER_ACCESS_REG   =   CSL_FMK (MDIO_USER_ACCESS_REG_PHYADR, userAccReg.phyAddr) |
                                                     CSL_FMK (MDIO_USER_ACCESS_REG_REGADR, userAccReg.regAddr) |
                                                     CSL_FMK (MDIO_USER_ACCESS_REG_WRITE, 0) |
                                                     CSL_FMK (MDIO_USER_ACCESS_REG_GO, 1u);

     // Wait for MDIO state machine finishing
     while (CSL_MDIO_isUserAccessPending (0));

     // Read result from USERACCESS register
     CSL_MDIO_getUserAccessRegister (0, &userAccReg);

     printf ("MDIO register 0x09 is 0x%04x\n", userAccReg.data);

}





From a recently powered up BCM5461 phy, I het the following outputs:

[C66xx_0] CSL_MDIO_isStateMachineEnabled() : 1
[C66xx_0] CSL_MDIO_isStateMachineIdle() : 0
[C66xx_0] CSL_MDIO_isPhyAlive(1) : 1
[C66xx_0] CSL_MDIO_isPhyLinked(1) : 1
[C66xx_0] CSL_MDIO_getHighestUserChannel() : 1
[C66xx_0] MDIO register 0x09 is 0x0300
[C66xx_0] MDIO register 0x09 is 0x1b00

Interestingly, our phy must be connected to a switch and then be resetted once more. Before that, no MDIO access is possible at all.

The SGMII link still does not come up, but I will ask that in a separate thread.

Regards,

Marcus

Thank you very much, The problem has been resolved.

I'm having a similar issue.  What was the solution?

Problem was that the ENABLE bit in the MDIO Control Register (0x02090304) was not set.