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port_ok of SRIO

guoping Lee
Expert 1010 points

Dear all

when I run the SRIO project in loopback mode on 6678evm, The port_ok bit will be right. But when I change the SRIO project in normal mode(send data to another DSP,but I do not connect my 6678evm to another 6678evm), the port_ok bit will not be seted. Do I have to connect the 6678evm to another 6678evm, or the port_ok bit will be wrong?  what should I do to make the port ok?thanks

  • 0
    TI__Intellectual 2790 points

    guoping Lee,

    If the port_ok is not set, that means the port has not been initialized. You will need to give a destination to that port, either external or internal. You can connect another 6678 EVM (external) or packet forward this port to another port in the same or other DSP (internal). 

    Thanks

    Elush Shirazpour 

    ------------------------------------------------------------------------------------------

    Please click Verify Answer if I have answered your question.

  • 0 in reply to Elush Shirazpour
    Expert 1010 points

    Hi Elush Shirazpour

    thank you for your reply. If I want to connect the 6678 to FPGA with SRIO. What should I do to make port_ok?

  • 0 in reply to guoping Lee
    TI__Intellectual 2790 points

    guoping Lee,

    You can find the answer to that and to complete an external loopback in other E2Es:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/181508/654400.aspx#654400

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/116866.aspx

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/116866/466307.aspx#466307

    Elush