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Is EDMA supported at MPAX mapped address?

Yang Beck
Prodigy 90 points


I use C6657 DSP. I set MSMCSRAM to non-cacheable by using MPAX register to map 0x0C000000 to a virtual address 0xD0000000 (1MB). It seems work. I can access address 0xD0000000 like memcpy function etc. But I found that I cannot perform EDMA to copy data from DDR to 0xD0000000.

Is something I missing? Or EDMA cannot be used at the MPAX mapped address?

  • 0
    TI__Expert 7180 points

    Hi Yang,

    To my best knowledge, we have two different types of MPAX.  One is located in the C66x core and explained in the section 7.3 XMC Memory Protection and Address eXtension (MPAX) of SPRUGW0B (http://www.ti.com/lit/ug/sprugw0b/sprugw0b.pdf).  On the other hand, when EDMA access the memory, it pass a different MPAX and it is explained in the section 2.2 Memory Protection and Address Extension (MPAX) of SPRUGW7A (http://www.ti.com/lit/ug/sprugw7a/sprugw7a.pdf).

    The following presentation material is also helpful to understand them.

    Especially, the diagram in the slide 29 (MPAX in the System) explains the above very well.

    I will double-check with coworkers but I guess the above is the reason what your observed.

    Best Regards,
    Atsushi

  • 0 in reply to Yokoyama, Atsushi
    Prodigy 90 points

    Hi Yokoyama,


    I use MPAX described in  section 7.3 of SPRUGW0B.

    So I need to use SES::MPAX described in section 2.2 of SPRUGW7A for using EDMA?

  • 0 in reply to Yang Beck
    Prodigy 90 points

    Another quesions,

    Is it slower for accessing MSMCSRAM via MPAX(or SES::MPAX) than directly accessing? And how slow it was? 

    And I found that L2 is always cached in L1D in C6657, that MAR register for L2 is fixed. 

    In my application I need to using EDMA for ping-pong buffering between DDR and L2, so I need to disable L2 cached in L1D.

    So its a right method that using MPAX mapping L2 to another virtual address? And accessing the virtual address will be very slow than directly accessing L2 address?

    How slow it was?

    Thanks for your response 

  • 0 in reply to Yang Beck
    TI__Expert 7180 points

    Yang,

    I'm afraid that I'm out of office today.  I will update ASAP.

    Best Regards,
    Atsushi

  • 0 in reply to Yokoyama, Atsushi
    Prodigy 90 points

    Hi Yokoyama,


     After I set the SES::MPAX register, the EDMA works for transferring data to MSMCSRAM, thank you.


    As described in TMS320C66x DSP Cache User Guide, C66x will automatic maintain the coherency between L1D and L2 when DMA accessing L2(snoop command), so its no need to disable cacheability of L2.

    But When I try it, I found the EDMA still not work for transferring data from DDR to L2, am I miss something again?

     

  • 0 in reply to Yang Beck
    TI__Expert 7180 points

    Yang,

    Sorry for my late replying.

    > So I need to use SES::MPAX described in section 2.2 of SPRUGW7A for using EDMA?

    Yes, you are correct.

    > Is it slower for accessing MSMCSRAM via MPAX(or SES::MPAX) than directly accessing? And how slow it was?

    I think the following application report will help.

    It is not linked from the C6657 website, but my understanding is it is also applicable to C6657.  Especially the Table 4 Memory Read Performance covers this topic.

    > As described in TMS320C66x DSP Cache User Guide, C66x will automatic maintain the coherency between L1D and L2 when DMA accessing L2(snoop command), so its no need to disable cacheability of L2.

    Yes, you are correct.

    > But When I try it, I found the EDMA still not work for transferring data from DDR to L2, am I miss something again?

    Could you clarify exact memory addresses which you tried, and also MPAX mapping?  Following is general guidelines.

    • When accessing memory by EDMA, it needs to use global access instead of "core local" memory address.  For example, accessing core #0 L2, we need to use 0x10800000 instead of 0x00800000.
    • As you already noticed, we need to take care of MPAX mapping in DSP core and also in MSMC.
    • Between L1D and core local L2 or shared L2 (only "SL2 mode" explained in the SPRABH2A above) are kept coherent automatically by cache controller, but regarding DDR or shared L2 (SL3 mode), we need to maintain cache coherency by manual cache write-back and invalidating operation.

    Regards,
    Atsushi

  • 0 in reply to Yokoyama, Atsushi
    Prodigy 90 points

    Hi Atsushi,


    I use local address 0x00800000 for DMA  before. After changing to global address, the EDMA works.

    Thanks for your great support!

  • 0 in reply to Yang Beck
    Intellectual 725 points

    Excuse me ,  could you tell me howdo you  set  SES::MPAX ?