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PIN_CONTROL_0 Register Access for GPIO 16~31 - GAUSS C6657

Hi,

  I am looking for similar requirement. I used CSL APIs to set direction and set output and clear output functions for GPIOs 16-31. I do not see any transaction. Can anyone advise what care we should take? If the registers described only for 0-15 bits (16 GPIOs), how do we access higher 16 GPIOs? 

I need GPIO_22, GPIO_25, GPIO_23, GPIO_27 and GPIO_16. I do not see any effect on any of these pins. 

Processor: C6657

APIs used:

void gpioSetDirection(uint32_t uiNumber, GpioDirection direction);
void gpioSetOutput(uint32_t uiNumber);
void gpioClearOutput(uint32_t uiNumber);

If I try to set the PIN_CONTROL_0 register - 0x02620580

After writing I see this register zero. 

Pl. advise what is that needed before accesssing these registers? 

volatile uint32_t *chipPinContrl_0=(volatile uint32_t *)0x02620580;
int gpioDbgCnt = 1000000;
void gpio_init(void)
{
uint32_t uint32_value;
uint32_value = *chipPinContrl_0; //CHIP_PIN_CONTROL_0;
uint32_value |= ( CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO17_TIM1_MASK |
CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO22_UARTCTS0_MASK |
CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO23_UARTRTS0_MASK |
CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO25_UARTTX1_MASK |
CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO27_UARTRTS1_MASK);
*chipPinContrl_0 = uint32_value;
//CHIP_PIN_CONTROL_0 = uint32_value;

  • Hari,

    The KICK registers may be locked in your setup, which protects the modification of boot configuration registers including PIN_CONTROL_0.

    Please refer to section 3.3.4 "Kicker Mechanism (KICK0 and KICK1) Register" in the C6657 data manual.

    You can add the KICK unlock code into your application to access the registers:

    volatile uint32_t *chipPinContrl_0=(volatile uint32_t *)0x02620580;
    int gpioDbgCnt = 1000000;
    #define KICK0 *(unsigned int*)(0x02620038)
    #define KICK1 *(unsigned int*)(0x0262003C)
    #define KICK0_UNLOCK (0x83E70B13)
    #define KICK1_UNLOCK (0x95A4F1E0)

    void gpio_init(void) {

    uint32_t uint32_value;

    //Unlock Boot Config Registers
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    uint32_value = *chipPinContrl_0; //CHIP_PIN_CONTROL_0;
    printf ("Before setup, PIN_CONTROL_0 register is 0x%x\n", *chipPinContrl_0);

    uint32_value |= ( CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO17_TIM1_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO22_UARTCTS0_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO23_UARTRTS0_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO25_UARTTX1_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO27_UARTRTS1_MASK);
    *chipPinContrl_0 = uint32_value;
    printf ("After setup, PIN_CONTROL_0 register is 0x%x\n", *chipPinContrl_0);
    }



  • Thanks. I shall try now. Do we need to lock after unlock/programming the PIN_CONTROL_0 register? 

    Also can you help me in toggling GPIO pins (16~31). As per the data sheet it covers lower 16 GPIOs only. 

    Regards,

    Hari

  • You can leave KICK unlocked if you have to access the boot configuration registers very often.

    But leave it locked will give the protection to those registers for any unexpected access.

    I think GPIO user guide needs to be updated for the 32 pins support. The functionality of 32-pin GPIO should be there for C6657.

    You can give a try with the following code to see if you can toggle GPIO_17, as you enabled it in PIN_CONTROL_0 register.

    #include <stdio.h>

    #include <stdint.h>
    #include "ti\csl\csl_gpio.h"
    #include "ti\csl\csl_gpioAux.h"
    #include "ti\csl\cslr_bootcfg.h"

    volatile uint32_t *chipPinContrl_0=(volatile uint32_t *)0x02620580;
    int gpioDbgCnt = 1000000;
    #define KICK0 *(unsigned int*)(0x02620038)
    #define KICK1 *(unsigned int*)(0x0262003C)
    #define KICK0_UNLOCK (0x83E70B13)
    #define KICK1_UNLOCK (0x95A4F1E0)

    void main(void) {

    uint32_t uint32_value;

    CSL_GpioHandle hGpio;
    uint32_t pinNum;
    Uint8 outData;

    //Unlock Boot Config Registers
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    uint32_value = *chipPinContrl_0; //CHIP_PIN_CONTROL_0;
    printf ("Before setup, PIN_CONTROL_0 register is 0x%x\n", *chipPinContrl_0);

    uint32_value |= ( CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO17_TIM1_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO22_UARTCTS0_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO23_UARTRTS0_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO25_UARTTX1_MASK |
    CSL_BOOTCFG_CHIP_PIN_CONTROL_0_GPIO27_UARTRTS1_MASK);
    *chipPinContrl_0 = uint32_value;
    printf ("After setup, PIN_CONTROL_0 register is 0x%x\n", *chipPinContrl_0);

    hGpio = CSL_GPIO_open (0); // Opens GPIO Instance 0

    pinNum = 17;
    CSL_GPIO_setPinDirOutput (hGpio, pinNum); //set GPIO_17 to be output

    CSL_GPIO_setOutputData (hGpio, pinNum); //set GPIO_17 to 1
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData); //get GPIO_17 output status
    printf("output of GPIO_%d is %d\n", pinNum, outData);

    CSL_GPIO_clearOutputData (hGpio, pinNum); //clear GPIO_17 to 0
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData); //get GPIO_17 output status
    printf("output of GPIO_%d is %d\n", pinNum, outData);

    }

  • Which CSL library do you include? CCS5.4 gives the errors that CSL_GPIOxxxx functions are not found in the library

  • Hi,

    CSL_GPIOxxxx functions are available in csl_gpioAux.h file. Those are part of PDK of C6657. 

    Please use the latest MCSDK 2.x released for Keystone I devices. Please find the download and user guide link below signature.

    We would recommend you to create new thread for faster response. Old threads will get less attention then new.

    Thank you.