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6678 boot core1 using core0

boot core1 using core0 on TMDXEVM6678LE,code is following:  

#define IPCGR_REG  ((volatile unsigned int*)0x02620240)
unsigned int magic=0x1187fffc;

    if(0 == corenum)
    {
     memcpy((void*)(0x11800000), (void*)0x00800000, 512*1024);

        // 0x1186d800 is the address of _c_int00 for core1 that caculated via _c_int00 address in .map file
        *((volatile unsigned int*)magic) = 0x1186d800 ;
        // Initialize main Platform lib
  memset(&init_config, 0, sizeof(platform_init_config));
  memset(&init_flags, 1, sizeof(platform_init_flags));
  if (platform_init(&init_flags, &init_config) != Platform_EOK)
  {
   printf ("Platform init failed!\n");
   print_platform_errno();
   return;
  }
  platform_uart_init();
  platform_uart_set_baudrate(BOOT_UART_BAUDRATE);
     /* sent IPC interrupt to core1 */
        IPCGR_REG[1] = 1;
  while(1)
  {
   for (i=0; i< 100000000; i++) ;
   write_uart(core_msg0);
  }
    }
    else if(1 == corenum)
    {
     while(1)
  {
   for (i=0; i< 100000000; i++) ;
   write_uart(core_msg1);
  }
    }
Question:

(1)0x1186d800 in the code is the address for _c_int00 in .map file  add 0x1100000, is it right ?
(2)when the code is loaded into core0 and run core0,it can print right message through UART, and I check the L2 of core1,the code is copied into L2 of core1.
(3)when the code is loaded into core0 and run core0,I check L2 via core1 ,the message is following,is it means core1 is interrupted by IPC ?


(4)when i check IPCGR_REG[1],value is 0. IPCGR_REG[1] is cleared after IPCGR_REG[1] is set 1 itself,is it right?
(5)why core1 can not be boot?

  • Hi,
    I'm not TI staff, so I can answer little.

    1) 0x1186d800 in the code is the address for _c_int00 in .map file  add 0x1100000, is it right ?
      right. but you may set only 0x0086d800 to MAGIC_ADDR, because core 1 jumps it's own L2SRAM. so the global address is not needed.
    2) don't copy memory to Core1's RBL's work area. Core1 runs RBL and using RBL's work area. about area, see datamanual.
    3) when the code is loaded into core0 and run core0,I check L2 via core1 ,the message is following,is it means core1 is interrupted by IPC ?
     sorry but I don't know. but i don't think so.
    4) You must UNLOCK KICK when writing to IPCGR
    5) why core1 can not be boot?
       forgetting Unlock kick and breaking Core1's RBL's work memory.

    I don't know but you might change boot mode to NOR or I2C from NO_BOOT(JTAG ONLY), because Core1's RBL may not watch IPC interrupt in NO_BOOT mode.

     

  •  Thanks for your help, the issue has been solved !

  • If you are willing, please explain your solution. I have been following this discussion with interest.

    Regards,
    RandyP

  • RandyP, the step is following :

    (1) copy the code from core0's L2SRAM  to core1's L2SRAM . the last 256 bytes are not been copied ,I am not sure why, I know the last 0xD32F bytes in L2SRAM is for boot ,but why  last 256 bytes can not be copied ?

    (2)Fill BOOT MAGIC ADDRESS using _c_int00's address. 

    (3) Unlock KICK

    (4) send IPC interupte

     

  • What method is doing the copy of code from CorePac 0 to CorePac 1?

  •  memcpy((void*)(0x11800000), (void*)0x00800000, 512*1024-512);

    to load the code into the core1