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Watchdog timer control register

Raymond Hermans
Prodigy 205 points
Other Parts Discussed in Thread: 66AK2H12

Hi,

After reading the Timer64P user guide (sprugv5a) the following question arose.

In the watchdog timer control register (WDTCR) there are two fields named WDKEY (table 5-7).
The first one (bit 31-16)  is used to put the watchdog timer in an active state and to service the watchdog.

The second one (bit 13-12) is described as the "idle enable key bits". I have found this to be the first and only place
where this is mentioned. Is this used to stop the watchdog timer when it is in active state or how should I interpret "idle mode"?

Thanks,

Raymond

  • 0
    TI__Intellectual 1585 points

    Hi Raymond, 

    So, bits 13-12 is as described the "idle" bits being enabled. It's a little confusing since those bits are called WDKEY as well.

    But, I believe "idle enabled" in this sense is basically saying that the timer is in watchdog mode, but not being used at this moment. An example would be, you've just reset after using your watchdog timer and have had interrupt, and now you would like to continue on in your code to say sending packets or etc. Sort of like the disable state in the  figure 4-2 in the user guide. 

    I hope this answers your question! Good luck with your programming. 

    -Kat Kelsch 

  • 0 in reply to Katherine Kelsch
    Prodigy 205 points

    Hi Kat,

    Thanks for the reply, but I still don't fully understand.

    What kind of reset are you talking about (Hard/Soft/Local)?
    When would you want to do this? Isn't putting the watchdog timer in pre-active state not the same as having the timer in watchdog mode and not using it?
    In what state (figure 4-2) will you (want to) do this and why?

    If you want to continue on in your code after a watchdog timeout, you can just ignore the interrupt right?
    As is the case for the 66AK2H12, if I understood the data manual correctly (sprs866) the default setting does not cause any output event of the Reset MUX
    and thus does not generate a reset (table 7-34 OMODE).

    I hope you can clarify this some more.

    Thanks,

    Raymond

  • 0 in reply to Raymond Hermans
    TI__Intellectual 1585 points

    Hey Raymond,

     

    Okay, so I consulted some of our internal documents on the Timer. I wanted to make sure I got the answer right, since I think I may have sounded incorrect.

     

    For your Question about the 13-12 bits:

      The 13-12 bits are actually called the WDIKEY instead of WDKEY. It appears the Use rguide forgot that one letter! Here is the excerpt:

    "The timer can be enabled/disabled to enter in the IDLE via a peripheral IDLE control bit. Once it enabled, the timer immediately enters in the IDLE state, i.e. stops counting, when the CPU has executed an IDLE instruction. This is achieved and controlled by an external clock gating logic. This logic utilizes an output signal, IDLEOUT, from the timer module that indicates the timer is ready to enter in the IDLE state (which is true all the time) and an input signal, IDLEIN, to the timer module to indicate the module is requested to be placed in IDLE state. When the timer is configured as a watchdog timer, it requires a write of 01b followed by a write of 10b into the register bits WDIKEY to enable the watchdog timer in IDLE mode. A write of 00b to the WDIKEY will disallow the watchdog timer goes into the IDLE mode.

    Once the watchdog is enabled, the timer cannot go into an IDLE state unless a proper key is written into the WDIKEY."

    And here's the state diagram for that:

    So, basically ignore about what I said about resets (FYI I was referring to hard resets) for that was incorrect. So, it can be in idle in both normal and watchdog mode. If you wanted to put your watchdog in a particular state, it depends on your code. You usually want to Start from the beginning state (inital state in the diagram) and just let it run until you get your interrupt you're looking for.

    When you would want to use IDLE state? Well I guess if you're using the watchdog multple times, it might be easier just to pause it with the idle state to prevent it from counting, or maybe if you want to just pause it. I honestly don't know of a common example, but I'll try to get one.

     For the OMODE default setting, you are correct. YOu have to assign the reset to the mux by triggering it that register. You can also do it in software in your interrupt vector.

    -Kat Kelsch

     

  • 0 in reply to Katherine Kelsch
    Prodigy 205 points

    Hi Kat,

    Thanks for the information!

    Raymond

  • 0 in reply to Katherine Kelsch
    Prodigy 205 points

    Hi Kat,

    I have been trying to pause the watchdog timer with the WDIKEY bits without succes.

    After the watchdog timer enters active state i send the following sequence of data to the WDTCR register:

    - 0xA5C61000
    - 0xA5C62000

    From your post describing the WDIKEY bits and state diagram I expected the watchdog timer to stop counting.
    Yet it seems to continue counting and eventualy trigger a watchdog timeout.
    Is this idle mode only applicable when the dedicated core of the watchdog timer is in idle or am I doing something wrong?

    I would like at a given moment to stop the watchdog timer from counting and later on be able to enable it again without a device reset in between.

    Is this possible?

    Thanks,

    Raymond 

  • 0 in reply to Raymond Hermans
    TI__Intellectual 1585 points

    Hi Raymond,

     

    I know that if you want your watchdog timer to switch from watchdog to general purpose (GP), you'd definitely need a reset. When it times out like that it usually is because it wasn't seriviced periodically by a on-chip timer or off chip. I'm assuming you're following all of the procedures mentioned in 4.4 of the timer user guide to set it up.

     

    The watchdog can only be disabled by a timeout event or a hardware reset. So, I don't believe you can just "pause" it unless you time it out, and restart it.  

     

    -Kat