We have a board that has a C6657 DSP connected to an FPGA via SRIO. We need the SRIO to run in x4 mode for required performance. When we power on / reset the board, then run the SRIO init software, the SRIO usually trains correctly. Intermittently, however, it trains to x1 mode. When that happens, we cannot recover unless we reset the DSP, which is an unacceptable solution.
We've tried everything we can think of on the FPGA side (reset SRIO, reset FPGA, reconfigure FPGA, etc.), but nothing worked.
We have software (residing in boot flash memory) that initializes the SRIO, checks and displays lane status, then resets the DSP. Like I mentioned above, it mostly trains correctly. Sometimes it trains to 1x and we can recover by re-running the init sequence (without resetting the DSP). After 16 of those re-initialization attempts, if it doesn't train to x4, we display a failure message. In either case, we reset the DSP to see what happens next.
When we see a failing case, the DSP reset always clears the error, and we are able to train the SRIO to x4.
I can go into more detail, if that would be helpful.
Thanks,
jw