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C6678 SRIO DMA Access Error

Brighton Feng
Expert 3410 points


Hi,

 

One of my customers connects C6678 to a FPGA through SRIO. They encountered “DMA Access Error” when FPGA tried to read from DSP.

The basic operation flow at FPGA is:

    NWRITE about 256KB to LL2 of DSP core 7

    NWRITE about 256KB to LL2 of DSP core 6

    ……

    NWRITE about 256KB to LL2 of DSP core 0

    NREAD the data just written in LL2 of DSP core 7, and verify it

    NREAD the data just written in LL2 of DSP core 6, and verify it

    ……

    NREAD the data just written in LL2 of DSP core 0, and verify it

 

The DSP is in a while waiting loop during this operation, that is, there is no any SRIO transfer start by DSP during this period.

 

The test passed on most boards. The problem only happened on several of their boards when they verified the data in LL2 of core 0, while the data was verified successfully on core 7~1.

 

I checked one of their failure board. On that board, the operation always failed at a fixed address 0x10847500 (in the middle of data blocks, data start from 0x10820000). The problem could be reproduced consistently. Below is the error information get from error status registers:

    Problem(RX_IO_DMA_ACCESS): A DMA access to the MAU was blocked (To clear this bit SW should write 0 to it)

    Reason & Solution: The Direct IO pkt request received by the RX side MAU, contained an invalid destination

                        address which is not accessible in the device memory map.                            

    Logical layer Error occurred in transaction from 0x0031 ---> 0x0041                                      

    DETAILS OF THE ERRONEOUS PKT:                                                                            

    PKT_TYPE   ---> NREAD packet                                                              

    DIO_XAMSBS ---> 0x00                                                                                     

    DIO_ADDRESS_MSB ---> 0x00000000                                                                          

    DIO_ADDRESS_LSB ---> 0x10847500                                                                           

    IMP_SPECIFIC---> 0x0000                                                                                  

 

The problem is, the captured address in the SRIO message is a valid address (0x10847500), why SRIO DMA access error is triggered?

 

The customer does not setup memory protection for LL2, that is, it is fully accessible by all masters.

 

Is there any other condition can trigger the SRIO “DMA access error”?

 

I searched SRIO user’s guide and found following description, does it have something to do with this issue?

But FPGA does not transfer any SRIO message, that is, RXU is not used.

 

    If the RXU descriptor dry out issue happens on a multisegment message that can't fit into the CDMA

    buffers, then the RXU is stalled. When the RXU is stalled, all channels are stalled, not

    just the one the channel with the dry out issue. If the condition lasts long enough, such

    that all the RX shared buffers of the logical layer are used, then other protocol units

    such as the TXU, LSU, MAU traffic is also blocked.

 

Thank you!

 

Brighton

 

  • 0
    TI__Mastermind 23525 points

    Brighton,

    Can you verify with CCS that the NWRITE values did get written into memory correctly when the fail occcurs?  I just want to know if the issue is truly on the NREAD side only.  If you can't verify with CCS, can you use NWRITE_R instead of NWRITE and look at the LSU completion code? 

    The DMA access error indicates an access attempt to either a non-mapped address, reserved address, or privledged/protected address.  Basically the internal bus returns an error to the SRIO peripheral for trying to access that address.  You mentioned no memory protection was being used, that would be my first thing to check.  Does the failing address cross any boundary, cache or otherwise?  Can you try using SRCID in the NWRITE/NREAD packet that equals the RIO_SUPRVSR_ID value?

    Regards,

    Travis

  • 0 in reply to tscheck
    TI__Expert 3410 points

    Hi, Travis,

    The NWRITE value is truly written into the memory by verifying it in CCS memory window.

    For the superior ID of DSP SRIO, we verify it is the same as the FPGA ID (0x31).

    As for the read address cross any boundary, cache or otherwise. We have test that the read will fail even the read size is 4byte (4byte aligned) at that specific LL2 address.

     Addtionally, we found a strange behavior, that, if we write full LL2 space and then read back the full space, we will not see the error.

    Could you give any suggestion to investigate it further?

    Thank you very much!

    Brighton

  • 0 in reply to Brighton Feng
    TI__Mastermind 23525 points

    Brighton,

    That is interesting but doesn't make sense to me.  If you can read the location once, you should be able to read it every time, unless you are reading with an invalid programmation of the LSU registers (this would cause a different CC for the LSU thought)  or reading from a memory protected area.  Do you have a repeatable testcase for the EVM that you can share?

    Regards,

    Travis