I get the uPP driver for C6657 from http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/202118.aspx
And I try to revise it as interrupt, according http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/270840/949136.aspx
But it can't enter UPP_ISR, anything wrong with my code below?
void upp_interrupt_setup(void)
{
/***************** interrupt configration for UPP **************************/
/* open CPINTC0 to map the UPP completetion ISR event to the host interrupt */
CSL_CPINTC_Handle hnd_UPP;
CSL_IntcEventHandlerRecord gpioHandler;
CSL_IntcParam vectId;
CSL_IntcHandle hIntcUpp;
CSL_IntcObj intcObjUpp;
hnd_UPP = CSL_CPINTC_open(0);
if (hnd_UPP == 0)
{
printf ("Error: Unable to open CPINTC-1\n");
return;
}
CSL_CPINTC_mapSystemIntrToChannel (hnd_UPP, CSL_INTC0_RPINT, 9);
CSL_CPINTC_enableSysInterrupt (hnd_UPP, CSL_INTC0_RPINT);
CSL_CPINTC_enableHostInterrupt (hnd_UPP, 9);
CSL_CPINTC_enableAllHostInterrupt(hnd_UPP);
vectId = CSL_INTC_VECTID_4;
hIntcUpp= CSL_intcOpen (&intcObjUpp, CSL_GEM_INTC0_OUT_9_PLUS_20_MUL_N, &vectId , NULL);
/* Bind ISR to Interrupt */
gpioHandler.handler = (CSL_IntcEventHandler)&upp_isr;
gpioHandler.arg = 0;
CSL_intcPlugEventHandler(hIntcUpp, &gpioHandler);
CSL_intcHwControl(hIntcUpp,CSL_INTC_CMD_EVTCLEAR,NULL);
/* Event Enable */
CSL_intcHwControl(hIntcUpp, CSL_INTC_CMD_EVTENABLE, NULL);
}
int upp_test()
{
int status = 0;
uppDevParams uPP;
upp_fill_buffer(xmtBuffer, dataWidth, UPP_DP_RJUST_0FILL, xferSize); // fill transmit buffer with test pattern
upp_fill_buffer(rcvBuffer, 0, UPP_DP_RJUST_0FILL, xferSize); // clear receive buffer
upp_key_config(); // program the KICK0 and 1 registers.
upp_pinmux_enable(); // Though internal loopback, enable uPP in PIN_CONTROL_1
// read PID
int pid = CSL_FEXT(uppRegs->UPPID, UPP_UPPID_REVID);
if(pid != CSL_UPP_UPPID_RESETVAL)
{
printf("\n Error : Incorrect UPP ID read.");
//goto upp_test_exit;
}
// toggle SW reset in PCR
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SWRST, RESET);
LOCAL_delay(200);
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SWRST, RUNNING);
// init regs: CTL, ICR, IVR, TCR
uPP = uppDevParams_DEFAULT;
uPP.A.direction = UPP_DIR_XMT;
uPP.A.dataRate = UPP_DR_SDR;//single data rate
uPP.A.dataWidthVal = dataWidth;
uPP.A.idleValueVal = 0xAAAA;
uPP.A.clkDivVal = 0x01; // use clock div between 0 and 0xF
uPP.A.txThresh = UPP_TT_64B;
uPP.B.direction = UPP_DIR_RCV;
uPP.B.dataRate = UPP_DR_SDR;
uPP.B.dataWidthVal = dataWidth;
uPP.B.idleValueVal = 0xBBBB;
uPP.B.clkDivVal = 0x01;
uPP.B.rcvThresh = UPP_TT_64B;
uPP.loopback = UPP_LB_INTERNAL;
uPP.numChannelsVal = 2;
status = upp_config(&uPP);
if (status < 0)
goto upp_test_exit;
// init interrupt regs
upp_interrupt_setup();
/***************** interrupt configration for UPP **************************/
upp_int_enable( upp_int_EOLI |
upp_int_EOWI |
upp_int_ERRI | upp_int_UORI | upp_int_DPEI |
upp_int_EOLQ |
upp_int_EOWQ |
upp_int_ERRQ | upp_int_UORQ | upp_int_DPEQ |
0 );
//transfer data
{
// Ensure uPP not enabled yet.
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, DISABLE);
// init DMA channels
while(CSL_FEXT(uppRegs->UPQS2, UPP_UPQS2_ACT) == 0)
upp_dma_prog(UPP_DMA_CHAN_Q, (void *)rcvBuffer, lineCnt, xferSize / lineCnt, xferSize / lineCnt);
while(CSL_FEXT(uppRegs->UPIS2, UPP_UPIS2_ACT) == 0)
upp_dma_prog(UPP_DMA_CHAN_I, (void *)xmtBuffer, lineCnt, xferSize / lineCnt, xferSize / lineCnt);
// Enable uPP here. PCR.EN bit
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, ENABLE);
status = 0;
}
upp_test_exit:
return status;
}