Hi,
I am unable to see interrupts reaching Core-1 from Core-0 using IPCGR.
I generate interrupt for every 5 msecs using generate_intr_2_core() function. But the ISR debug counter never increments.
Please advise.
Regards,
Hari
The following is my code snippet.
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/********* RTSC configuration file ----- test.CFG: ******************/
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var hwi1Params = new Hwi.Params();
hwi1Params.instance.name = "HWI_Inter_core_Isr";
hwi1Params.eventId = 12;
Program.global.HWI_Inter_core_Isr = Hwi.create(6, "&core_2_core_hwi_Isr", hwi1Params);
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/*********** SOURCE FILE *************************/
#define CHIP_LEVEL_REG 0x02620000
#define KICK0 (CHIP_LEVEL_REG + 0x0038)
#define KICK1 (CHIP_LEVEL_REG + 0x003C)
#define IPCGR(x) (0x02620240 + x*4)
int core_2_core_Isr_cnt=0;
void core_2_core_Isr(void)
{
core_2_core_Isr_cnt++;
}
int core_2_core_hwi_Isr_cnt=0;
void core_2_core_hwi_Isr(void)
{
core_2_core_hwi_Isr_cnt++;
}
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void generate_intr_2_core(void)
{
*((volatile unsigned int *)KICK0)=0x83e70b13;
*((volatile unsigned int *)KICK0)=0x95a4f1e0;
*((volatile unsigned int *)IPCGR(1))=1;
//*((volatile unsigned int *)IPCGR(1))=1;
//CSL_IPC_genGEMInterrupt( 1, 0 );
//hIpc->IPCGR[index] = CSL_FMK (IPC_IPCGR_IPCG, 1) |
// CSL_FMKR (CSL_IPC_IPCGR_SRCS0_SHIFT + srcId, CSL_IPC_IPCGR_SRCS0_SHIFT + srcId, 1);
}
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void core_2_core_interrupt(void)
{
CpIntc_dispatchPlug(CSL_GEM_IPC_LOCAL, (CpIntc_FuncPtr)core_2_core_Isr, CSL_GEM_IPC_LOCAL, TRUE);
CpIntc_mapSysIntToHostInt(0, CSL_GEM_IPC_LOCAL, 12);
CpIntc_enableHostInt(0, 12);
CpIntc_enableSysInt(0, CSL_GEM_IPC_LOCAL);
}
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