Hi,
We're trying (for quite some time now) to get the IPC Messaging working over SRIO with more than 2 cores active per chip, using two EVM6678 and a breakout board.
I used the srioIpcChipToChipExample supplied with the PDK as a starting point which works well as is (two cores per chip sending messages). However, as soon as 3 or more cores per chip are configured, SRIO is messed up.
Although initialization seems to be successful, the NameServerMessageQ is not functional and fails to resolve remote message-queue IDs.
We used EVMs for better reproducibility, but it behaves exactly the same on the final target hardware.
After digging for more information, we found the following, unfourtunately unanswered, post describing what sounds like the same issue: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/284083/996887.aspx
I've uploaded the output with 3 cores active here: http://pastebin.com/PdLPSMCt
The modified srioChipToChip example project can be downloaded here: 4274.srioIpcChipToChipExample3Cores.zip
We really need assistance with this issue, due to the time already lost trying to get it working it isbecoming critical for our project.
Thank you in advance, Clemens
Versions used:
XDCTools-3.25.4.60
CGT-7.4.2
IPC-1.24.3.32
PDK: 1.1.2.6
SYS/BIOS: 6.35.4.50