XTCIEVMK2X Rev1.0: ARM view and DSP view of DDR3A and DDR3B

Rams

Other Parts Discussed in Thread: TCI6638K2K

This is regarding the ARM view and DSP view of DDR3A and DDR3B. It is still not clear after going through the below post on DDR3A and DDR3B mapping and ARM and DSP view.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/300548/1058399.aspx#1058399

The XTCIEVMK2X Rev1.0 is mounted with 2GB DDR3 DIMM as DDR3A and 1GB of DDR3B.

My questions are:

1. U-Boot detects only 1GB of DDR3, is that DDR3A or DDR3B??

If it is DDR3A, why it shows only 1GB?

U-Boot SPL 2013.01-dirty (Nov 25 2013 - 11:19:53)
SF: Detected N25Q128A with page size 64 KiB, total 16 MiB

U-Boot 2013.01-dirty (Nov 25 2013 - 11:19:53)

I2C: ready
Detected SO-DIMM [ǧSQR-SD3T-2G1333]
DRAM: 1 GiB
NAND: 512 MiB
Net: TCI6638_EMAC, TCI6638_EMAC1
Hit any key to stop autoboot: 0

2. From the datasheet, page number 94, SPRS866E November 2013,

Let us first assume the scenario where DDR3A_REMAP_EN pin is '0' which is default settings in the EVM,

The physical memory 00 6000 0000 to 00 7ffff ffff (512M) from ARM view refers to DDR3B data which is same as that of 00 8000 0000 to 00 9ffff ffff as this is aliased of 00 8000 0000 to 00 9ffff ffff (the first 512MB of DDR3B)

The physical memory 00 8000 0000 to 00 FFFF FFFF (2G) from ARM view will be DDR3B data as DDR3A_REMAP_EN pin is '0'. DSP view will be DDR3B data.

The kernel load address and u-boot CONFIG_SYS_SDRAM_BASE points to 0x80000000

Therefore, in this case, does that mean the EVM uses only DDR3B for both ARM and DSP?

2. Given the DDR3A and DDR3B sizes for EVM, it would be nice to know the ARM view and DSP view of address ranges, with and without DDR3A_REMAP_EN pin enabled.

Target chip : TCI6638k2k

Target EVM : XTCIEVMK2X Rev1.0

CCS ver : CCS 5.4.0.00091

MCSDK version:

mcsdk_bios_3_00_01_12

mcsdk_linux_3_00_01_12

over 11 years ago

0 Rex Chang over 11 years ago

TI__Guru 50170 points

Hi, Ram,

The DRAM size shown in U-boot is DDR3A memory and because of a hardware issue, only half of the memory can be detected in Rev 1.0/1.1 EVM. This issue has been corrected in Rev 2.0 EVM with new silicon.

The DDR3A_REMAP_EN signal is default to be pull down (page 39) which I believe in software means 1. Hence, for ARM, DDR3B is at 0x6000 0000, and DDR3A at 0x8000 0000.

As what were said, 0x6000 0000 region is DDR3B for both ARM and DSP. 0x8000 0000 is DDR3B for DSP, but DDR3A for ARM which maps to the 1st 2GB of the 8GB DDR3A memory starting at 0x08 0000 0000. The difference is that when using 32-bit addressing to refer to this 2 GB memory, it does not support IO coherency, while 36-bit addressing to the same area does.

Hope this clarifies your questions.

Rex

0 Rams over 11 years ago in reply to Rex Chang

Expert 1800 points

Hi Rex,

Does this mean that the DSP view of 0x6000 0000 to 0x7FFF FFFF and 0x8000 000 to 0x9FFF FFFF are the same locations of DDR3B given DDR3A_REMAP_EN pin is 1.?

Regards

Ram

0 steve zhang over 11 years ago in reply to Rex Chang

Expert 1690 points

Hi,Rex:

In the datasheet SPRS836A memory map section.

what does this mean?

I cannot understand.what does that mean?

That seems that address range from 0x60000000 to 0x7fffffff is aliased of 0x8000 0000 to

0x9fff ffff. But what dose that mean?

what does" aliased" mean?

0 Rex Chang over 11 years ago in reply to Rams

TI__Guru 50170 points

Hi, Ram,

The way I interpret the data sheet is that the DDR3A_REMAP_EN does not play any role in DSP view, and yes, the first 512MB are the same location using 0x6000 0000 or 0x8000 0000 (regardless REMAP_EN) according to note 4.

Rex

0 Rex Chang over 11 years ago in reply to steve zhang

TI__Guru 50170 points

Hi, Steve,

I think your data sheet may be a bit older than the one I am looking at. Mine is SPRS866E, and yours probably version D, so the note nubers are off. Any way, alias by definition is "

used to indicate that a named person is also known or more familiar under another specified name." from google and "also called, or otherwise known as" from Merriam-Webster dictionary.

So, that means the same location can be addressed either using 0x6000 0000 or 0x8000 0000, but it onlly applies to the first 512MB as the address range indicated in the data sheet.

Rex

0 Rams over 11 years ago in reply to Rex Chang

Expert 1800 points

Hi Rex,

Thanks for your clarification.

There is one question which remains unanswered from you which I had raised, that is what Steve also has been raising in this post. When DDR3A_REMAP_EN pin is zero, the address ranges 0x6000 0000 to 0x7FFF FFFF (512M) from ARM view points to DDR3B data and DSP view also points to DDR3B data which means DDR3A is not used. Does this mean, DDR3A will not be accessed when DDR3A_REMAP_EN pin is zero?

3 This region is mapped to DDR3B. It is aliased of 00 8000 0000 to 00 9FFF FFFF (the first 512MB of DDR3B) if the state of DDR3A_REMAP_EN pin at boot time is ‘0’.

Kindly clarify

Regards

Rams

0 Rex Chang over 11 years ago in reply to Rams

TI__Guru 50170 points

Hi, Ram,

Ok. So we are clear with DSP view. From ARM's view, if REMAP_EN is 0, then 0x8000 0000 is mapped to 2GB of DDR3B memory. The DDR3A can still be accessed through 0x08 0000 0000. This means 0x8000 0000 is not overlaid onto 0x08 0000 0000 any more. Hope this clarifies it.

Rex

0 Rams over 11 years ago in reply to Rex Chang

Expert 1800 points

Hi Rex,

Theoretically, it seems to be right. You say that 0x8000 0000 is not overlaid onto 0x08 0000 0000 and DDR3A can still be accessed through 0x08 0000 0000. But u-boot start address is set to 0x8000 0000 and when REMAP_EN is 0, u-boot will always be started in DDR3B and not in DDR3A. Is this right?

Regards

Rams

0 Rex Chang over 11 years ago in reply to Rams

TI__Guru 50170 points

Hi, Rams,

I would say yes (theoretically), but we have not tried it and can't remove the theoretically part from the sentence. From your other post, the start address of u-boot is to where the u-boot will relocate itself from MSMC. It should not matter if it is 3A or 3B memory, nor starts from 0x6000 0000 or 0x8000 0000, should it?

Rex

0 Rams over 11 years ago in reply to Rex Chang

Expert 1800 points

Hi Rex,

Thanks for your response. This is exactly we are trying to understand and know the behaviour for our system design. How do we know that we should set REMAP_EN to 0 or 1? How does this impact on system memory map if we set it to 0 or 1?. If we set REMAP_EN to 0 on our custom design, I should be able to predict the impact on our system and the memory map. And, I would like to do some experiments with EVM to check all these.

Hope you would appreciate the importance of establishing the theoretical facts.

Thanks

Rams

0 Rex Chang over 11 years ago in reply to Rams

TI__Guru 50170 points

Hi, Rams,

Please check data sheet. REMAP_EN pin is shared with GPIO16, and also the BMC In-field Update, http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup#DIP_Switch_and_Bootmode_Configurations, in which it defines different boot mode. Bit 20 shows the config Pin function, the REMAP_EN, and the Normal Pin function, GPIO16.

I set a user bootmode with bit 20 set to 0 (REMAP_EN), and was able to bring up u-boot, but not kernel because tftp failed to get the images (3A memory conflict?). I did a memory dump and I captured all my actions in the log file (attached). Please take a look and let me know if you have any questions.

Fullscreen 6116.boot.log Download


Changing REMAP_EN pin 
=====================

[21:23:01]  BMC>bootmode
[21:23:01]  Executing command "bootmode"
[21:23:01]  Current Bootmode is 0x0000000000112005   ARM SPI
[21:23:46]  BMC>bootmode all
[21:23:46]  Executing command "bootmode"
[21:23:46]   0 0x0000000000110CE7   ARM NAND
[21:23:46]   1 0x0000000000100001   DSP No-Boot
[21:23:46]   2 0x0000000000112005   ARM SPI......Current Bootmode
[21:23:46]   3 0x0000000000100003   ARM I2C
[21:23:46]   4 0x0000000000100CEF   ARM UART
[21:23:46]   5 0x0000000000111CEB   ARM RBL ENET
[21:23:46]   6 0x00000000001010E1   SLEEP W/ MAX PLL & ARM BYPASS
[21:23:46]   7 0x0000000000103EE1   SLEEP W/ MAX PLL
[21:23:46]   8 0x00000000001101E7   DSP NAND
[21:23:46]   9 0x00000000001010C1   SLEEP W/ SLOW PLL & ARM BYPASS
[21:23:46]  10 0x0000000000112105   DSP SPI
[21:23:46]  11 0x0000000000100103   DSP I2C
[21:23:46]  12 0x0000000000100DEF   DSP UART
[21:23:46]  13 0x00000000001111EB   DSP RBL ENET
[21:23:46]  14 0x0000000000103CC1   SLEEP W/ SLOW PLL & SLOW ARM PLL
[21:23:46]  15 0x0000000000100001   DSP No-Boot
[21:34:28]  BMC>bootmode 8 0 012005 ARM_B_SPI
[21:34:28]  Executing command "bootmode"
[21:34:28]  Changing User Bootmode 8 to 0x0000000000012005 arm_b_spi , this change is volatile
[21:34:35]  BMC>bootmode
[21:34:35]  Executing command "bootmode"
[21:34:35]  Current Bootmode is 0x0000000000112005   ARM SPI
[21:34:59]  BMC>bootmode all
[21:34:59]  Executing command "bootmode"
[21:34:59]   0 0x0000000000110CE7   ARM NAND
[21:34:59]   1 0x0000000000100001   DSP No-Boot
[21:34:59]   2 0x0000000000112005   ARM SPI......Current Bootmode
[21:34:59]   3 0x0000000000100003   ARM I2C
[21:34:59]   4 0x0000000000100CEF   ARM UART
[21:34:59]   5 0x0000000000111CEB   ARM RBL ENET
[21:34:59]   6 0x00000000001010E1   SLEEP W/ MAX PLL & ARM BYPASS
[21:34:59]   7 0x0000000000103EE1   SLEEP W/ MAX PLL
[21:34:59]   8 0x0000000000012005   arm_b_spi
[21:34:59]   9 0x00000000001010C1   SLEEP W/ SLOW PLL & ARM BYPASS
[21:34:59]  10 0x0000000000112105   DSP SPI
[21:34:59]  11 0x0000000000100103   DSP I2C
[21:34:59]  12 0x0000000000100DEF   DSP UART
[21:34:59]  13 0x00000000001111EB   DSP RBL ENET
[21:34:59]  14 0x0000000000103CC1   SLEEP W/ SLOW PLL & SLOW ARM PLL
[21:34:59]  15 0x0000000000100001   DSP No-Boot
[21:35:22]  BMC>bootmode #8
[21:35:22]  Executing command "bootmode"
[21:35:22]  Changing to bootmode 8: arm_b_spi
[21:35:25]  BMC>bootmode
[21:35:25]  Executing command "bootmode"
[21:35:25]  Current Bootmode is 0x0000000000012005   arm_b_spi
BMC>
[21:35:25]  Current Bootmode is 0x0000000000012005   arm_b_spi
[21:36:12]  BMC>reboot
[21:36:12]  Executing command "reboot"
[21:36:12]  Full Reset Begin
[21:36:12]  Full Reset Complete
[21:36:12]  SOC RST Begin
[21:36:12]  Current BootMode is set to arm_b_spi
[21:36:12]  SOC RST Complete
[21:36:13]  BOOT COMPLETE


Memory display after u-boot comes up with REMAP_EN set to 0
===========================================================

(Note: 0x6000 8000 and 0x8000 8000 has same content)

TCI6638 EVM # md 0x80000000
80000000: 00000000 00000000 55555555 55555555    ........UUUUUUUU
80000010: 00000000 00000000 00000000 00000000    ................
80000020: 55555555 55555555 00000000 00000000    UUUUUUUU........
80000030: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
80000040: 00000000 00000000 55555555 55555555    ........UUUUUUUU
80000050: 00000000 00000000 00000000 00000000    ................
80000060: 55555555 55555555 00000000 00000000    UUUUUUUU........
80000070: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
80000080: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
80000090: 00000000 00000000 00000000 00000000    ................
800000a0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
800000b0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
800000c0: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
800000d0: 00000000 00000000 00000000 00000000    ................
800000e0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
800000f0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
TCI6638 EVM # md 0x60000000
60000000: 00000000 00000000 55555555 55555555    ........UUUUUUUU
60000010: 00000000 00000000 00000000 00000000    ................
60000020: 55555555 55555555 00000000 00000000    UUUUUUUU........
60000030: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
60000040: 00000000 00000000 55555555 55555555    ........UUUUUUUU
60000050: 00000000 00000000 00000000 00000000    ................
60000060: 55555555 55555555 00000000 00000000    UUUUUUUU........
60000070: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
60000080: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
60000090: 00000000 00000000 00000000 00000000    ................
600000a0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
600000b0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
600000c0: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
600000d0: 00000000 00000000 00000000 00000000    ................
600000e0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
600000f0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
TCI6638 EVM # md 80008000
80008000: ebfffffb f7ffec72 b9c057b5 57cea14a    ....r....W..J..W
80008010: 9af57eff 6bf670d6 dbddffff 7fff9722    .~...p.k...."...
80008020: 28a2adfe fdff8682 a7e7eff7 fbff9579    ...(........y...
80008030: e7ffffff dffd778f 3c807b6e e7be4c90    .....w..n{.<.L..
80008040: edff6bff ffff1a75 1c137ea3 56f50005    .k..u....~.....V
80008050: ef0d0d5d fefe9523 f3d5fdff fffb78ec    ]...#........x..
80008060: b8f37f2f beefa4a6 ef7dbf62 6ffbc37d    /.......b.}.}..o
80008070: fddbf7ff bfffa7ef adb6e8f7 f7f98688    ................
80008080: ffafffff ff7fdff8 5ac67ff4 d3ba086f    ...........Zo...
80008090: aa99ebfa dbb71172 fef7fffb fefdfe26    ....r.......&...
800080a0: afb7ea7f dc766293 f7ef7fff f7bf7ff1    .....bv.........
800080b0: fbffffff bff7dfb3 eaf628d7 b6d01413    .........(......
800080c0: fefffeff ef7f78fe 8536df0f a76a042b    .....x....6.+.j.
800080d0: f7a6fefd bf3d355a dfbfefef df5fd7e0    ....Z5=......._.
800080e0: c6bfb7cd faf59ac9 f5effffe ffff3ec4    .............>..
800080f0: 6efffd73 fffffffd d6f1d3bd dc759438    s..n........8.u.
TCI6638 EVM # md 0x60008000
60008000: ebfffffb f7ffec72 b9c057b5 57cea14a    ....r....W..J..W
60008010: 9af57eff 6bf670d6 dbddffff 7fff9722    .~...p.k...."...
60008020: 28a2adfe fdff8682 a7e7eff7 fbff9579    ...(........y...
60008030: e7ffffff dffd778f 3c807b6e e7be4c90    .....w..n{.<.L..
60008040: edff6bff ffff1a75 1c137ea3 56f50005    .k..u....~.....V
60008050: ef0d0d5d fefe9523 f3d5fdff fffb78ec    ]...#........x..
60008060: b8f37f2f beefa4a6 ef7dbf62 6ffbc37d    /.......b.}.}..o
60008070: fddbf7ff bfffa7ef adb6e8f7 f7f98688    ................
60008080: ffafffff ff7fdff8 5ac67ff4 d3ba086f    ...........Zo...
60008090: aa99ebfa dbb71172 fef7fffb fefdfe26    ....r.......&...
600080a0: afb7ea7f dc766293 f7ef7fff f7bf7ff1    .....bv.........
600080b0: fbffffff bff7dfb3 eaf628d7 b6d01413    .........(......
600080c0: fefffeff ef7f78fe 8536df0f a76a042b    .....x....6.+.j.
600080d0: f7a6fefd bf3d355a dfbfefef df5fd7e0    ....Z5=......._.
600080e0: c6bfb7cd faf59ac9 f5effffe ffff3ec4    .............>..
600080f0: 6efffd73 fffffffd d6f1d3bd dc759438    s..n........8.u.


U-boot using REMAP_EN being 1
=============================

(Note: 0x6000 8000 has different content as 0x8000 0000)
Is this a proof of 3B vs 3A memory?


TCI6638 EVM # md 0x60008000
60008000: ffffffff ffff4040 ffffffff ffff0000    ....@@..........
60008010: ffffffff ffff2000 ffffffff ffff0000    ..... ..........
60008020: ffffffff ffff0000 ffffffff ffff0028    ............(...
60008030: ffffffff ffff000e ffffffff ffff0000    ................
60008040: ffffffff ffff1061 ffffffff ffff0000    ....a...........
60008050: ffffffff ffff0001 ffffffff ffff0000    ................
60008060: ffffffff ffff8082 ffffffff ffff0000    ................
60008070: ffffffff ffff0029 ffffffff ffff0000    ....)...........
60008080: ffffffff ffff0000 ffffffff ffff0000    ................
60008090: ffffffff ffff0000 ffffffff ffff0200    ................
600080a0: ffffffff ffff0000 ffffffff ffff00c0    ................
600080b0: ffffffff ffff0033 ffffffff ffff0001    ....3...........
600080c0: ffffffff ffff7800 ffffffff ffff0000    .....x..........
600080d0: ffffffff ffff0000 ffffffff ffff0400    ................
600080e0: ffffffff ffff0000 ffffffff ffff0040    ............@...
600080f0: ffffffff ffff0810 ffffffff ffff0010    ................
TCI6638 EVM # md 0x80008000
80008000: f1dfdde4 f3fffc39 e32fe47f ffdfd85f    ....9...../._...
80008010: f7ef9cdd fbeb9fbf fffdd477 7f9170f7    ........w....p..
80008020: f3efdedd f7bfe0bc fffffecd fb3fffff    ..............?.
80008030: f77f97ef e3bbf6a9 ffdfdf5c efff7fdf    ........\.......
80008040: ebf8ec1d 3fbfddff fff1ffff f7fff9ef    .......?........
80008050: f777a7ff 7f7fddfb e7fffd71 fbbf85b2    ..w.....q.......
80008060: ebebe675 fbff98df ffdede79 fb7bcfff    u.......y.....{.
80008070: eb3676df ef6bd7e7 fdffd37d efafef6f    .v6...k.}...o...
80008080: f7b787ff e7aff35c fffcfde7 e76ff87f    ....\.........o.
80008090: dfa2d5dc f6b87c23 fbb9fbaf e9f1e375    ....#|......u...
800080a0: e7e5f504 f7ff7be5 ffaa368e f7d374af    .....{...6...t..
800080b0: f5d5bc7c ffcaffbd ffbb0d96 7ffffffb    |...............
800080c0: e3ff7bf5 f2bd3ba3 e78f78e7 f7b366bc    .{...;...x...f..
800080d0: e7fbfd2f f69f331e f7ccf78f fbe37a15    /....3.......z..
800080e0: e3fee795 7bffffff e2f65f41 ffbff7be    .......{A_......
800080f0: f3dfe9fd ff9bcc7d f3437e2f ffefdfaa    ....}.../~C.....

Rex

0 Rams over 11 years ago in reply to Rex Chang

Expert 1800 points

Hello Rex,

Thanks a lot for your patience in answering all the queries. I will come back to you if I have further questions.

Thanks

Rams

0 steve zhang over 11 years ago in reply to Rex Chang

Expert 1690 points

Rex Chang said:

Hi, Steve,

I think your data sheet may be a bit older than the one I am looking at. Mine is SPRS866E, and yours probably version D, so the note nubers are off. Any way, alias by definition is "

used to indicate that a named person is also known or more familiar under another specified name." from google and "also called, or otherwise known as" from Merriam-Webster dictionary.

So, that means the same location can be addressed either using 0x6000 0000 or 0x8000 0000, but it onlly applies to the first 512MB as the address range indicated in the data sheet.

Rex

Hi Rex:

where can I get the latest datasheet SPRS866E ?I find Rams have used the latest one.

But when I search in the google,nothing appears.

0 Rams over 11 years ago in reply to steve zhang

Expert 1800 points

Hi Steve,

I used the below link

http://www.ti.com/lit/ds/symlink/66ak2h06.pdf

Regards

Rams

0 Rams over 11 years ago in reply to Rex Chang

Expert 1800 points

Hello Rex,

I have two EVM kits 1.0 and 2.0. I tried to check the behavior on both of my kits.

Below are the observations:

1. EVM 1.0 does gets hung during DRAM initialization when REMAP_EN bit is set to zero using the commands on BMC prompt. Please find the attached logs of BMC console.

Fullscreen 1513.bmc_log_evm1_0.txt Download

[00:02:28]  BMC>bootmode
[00:02:28]  Executing command "bootmode"
[00:02:28]  Current Bootmode is 0x0000000000112005   ARM SPI
[00:02:36]  BMC>bootmode all
[00:02:36]  Executing command "bootmode"
[00:02:36]   0 0x0000000000110CE7   ARM NAND
[00:02:36]   1 0x0000000000100001   DSP No-Boot
[00:02:36]   2 0x0000000000112005   ARM SPI......Current Bootmode
[00:02:36]   3 0x0000000000100003   ARM I2C
[00:02:36]   4 0x0000000000100CEF   ARM UART
[00:02:36]   5 0x0000000000111CEB   ARM RBL ENET
[00:02:36]   6 0x00000000001010E1   SLEEP W/ MAX PLL & ARM BYPASS
[00:02:36]   7 0x0000000000103EE1   SLEEP W/ MAX PLL
[00:02:36]   8 0x00000000001101E7   DSP NAND
[00:02:36]   9 0x00000000001010C1   SLEEP W/ SLOW PLL & ARM BYPASS
[00:02:36]  10 0x0000000000112105   DSP SPI
[00:02:36]  11 0x0000000000100103   DSP I2C
[00:02:36]  12 0x0000000000100DEF   DSP UART
[00:02:36]  13 0x00000000001111EB   DSP RBL ENET
[00:02:36]  14 0x0000000000103CC1   SLEEP W/ SLOW PLL & SLOW ARM PLL
[00:02:36]  15 0x0000000000100001   DSP No-Boot
[00:02:46]  BMC>bootmode 8 0 012005 ARM_B_SPI
[00:02:46]  Executing command "bootmode"
[00:02:46]  Changing User Bootmode 8 to 0x0000000000012005 arm_b_spi , this change is volatile
[00:02:53]  BMC>bootmode all
[00:02:53]  Executing command "bootmode"
[00:02:53]   0 0x0000000000110CE7   ARM NAND
[00:02:53]   1 0x0000000000100001   DSP No-Boot
[00:02:53]   2 0x0000000000112005   ARM SPI......Current Bootmode
[00:02:53]   3 0x0000000000100003   ARM I2C
[00:02:54]   4 0x0000000000100CEF   ARM UART
[00:02:54]   5 0x0000000000111CEB   ARM RBL ENET
[00:02:54]   6 0x00000000001010E1   SLEEP W/ MAX PLL & ARM BYPASS
[00:02:54]   7 0x0000000000103EE1   SLEEP W/ MAX PLL
[00:02:54]   8 0x0000000000012005   arm_b_spi
[00:02:54]   9 0x00000000001010C1   SLEEP W/ SLOW PLL & ARM BYPASS
[00:02:54]  10 0x0000000000112105   DSP SPI
[00:02:54]  11 0x0000000000100103   DSP I2C
[00:02:54]  12 0x0000000000100DEF   DSP UART
[00:02:54]  13 0x00000000001111EB   DSP RBL ENET
[00:02:54]  14 0x0000000000103CC1   SLEEP W/ SLOW PLL & SLOW ARM PLL
[00:02:54]  15 0x0000000000100001   DSP No-Boot
[00:03:01]  BMC>bootmode #8
[00:03:01]  Executing command "bootmode"
[00:03:01]  Changing to bootmode 8: arm_b_spi
[00:03:14]  BMC>
[00:03:19]  BMC>bootmode
[00:03:19]  Executing command "bootmode"
[00:03:19]  Current Bootmode is 0x0000000000012005   arm_b_spi
[00:03:30]  BMC>reboot
[00:03:30]  Executing command "reboot"
[00:03:30]  Full Reset Begin
[00:03:30]  Full Reset Complete
[00:03:30]  SOC RST Begin
[00:03:30]  Current BootMode is set to arm_b_spi
[00:03:30]  SOC RST Complete
[00:03:30]  BOOT COMPLETE

When I reboot, the u-boot does not come up, stops in DRAM init.

2. With EVM 2.0, by setting REMAP_EN bit is set to zero, the U-Boot starts up.  The dump of 0x8000 0000 and 0x6000 0000 is same and there is no change irrespective of REMAP_EN bit 0 or 1.

TCI6638 EVM # md 0x80000000
80000000: 00000000 00000000 55555555 55555555    ........UUUUUUUU
80000010: 00000000 00000000 00000000 00000000    ................
80000020: 55555555 55555555 00000000 00000000    UUUUUUUU........
80000030: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
80000040: 00000000 00000000 55555555 55555555    ........UUUUUUUU
80000050: 00000000 00000000 00000000 00000000    ................
80000060: 55555555 55555555 00000000 00000000    UUUUUUUU........
80000070: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
80000080: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
80000090: 00000000 00000000 00000000 00000000    ................
800000a0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
800000b0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
800000c0: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
800000d0: 00000000 00000000 00000000 00000000    ................
800000e0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
800000f0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
TCI6638 EVM # md 0x60000000
60000000: 00000000 00000000 55555555 55555555    ........UUUUUUUU
60000010: 00000000 00000000 00000000 00000000    ................
60000020: 55555555 55555555 00000000 00000000    UUUUUUUU........
60000030: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
60000040: 00000000 00000000 55555555 55555555    ........UUUUUUUU
60000050: 00000000 00000000 00000000 00000000    ................
60000060: 55555555 55555555 00000000 00000000    UUUUUUUU........
60000070: 55555555 55555555 55555555 55555555    UUUUUUUUUUUUUUUU
60000080: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
60000090: 00000000 00000000 00000000 00000000    ................
600000a0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
600000b0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................
600000c0: 00000000 00000000 aaaaaaaa aaaaaaaa    ................
600000d0: 00000000 00000000 00000000 00000000    ................
600000e0: aaaaaaaa aaaaaaaa 00000000 00000000    ................
600000f0: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa    ................

Please clarify

Regards

Rams

0 Rams over 11 years ago in reply to Rams

Expert 1800 points

Hi Rex,

The BMC version on both the kits are 1.0.2.5

Regards

Rams

0 steve zhang over 11 years ago in reply to Rams

Expert 1690 points

Hi,Rams:

Thanks! I get it.

0 Rams over 11 years ago in reply to Rams

Expert 1800 points

Hello Rex,

Sorry for my previous post where I had reported that Rev2.0 does not show the expected behaviour. I did further testing with Rev2.0 and tried modifying and dumping different memory ranges from 0x6000 0000 and 0x8000 0000 with REMAP_EN bit ON and OFF. It works as expected.

But Rev 1.0 doesnt work for me. Do you know why the U-boot doesnt startup with EVM REV1.0 if REMAP_EN bit is set to zero?

Regards

Ram

0 steve zhang over 11 years ago in reply to Rams

Expert 1690 points

Hi,Rams:

Can you tell me directly that the value of DDR3A_REMAP_EN is 0 or 1 when EVM power up?

I want to know that value for rather long time.But I cannot get sure answer.

I just know that when EVM power up.the pin of DDR3A_REMAP_EN is pulled down.

I only can guess that value .0?1?1?0? .......

Rex said 1.Do you think ? How to prove that?

0 Rams over 11 years ago in reply to steve zhang

Expert 1800 points

Hi Steve,

You are right DDR3A_REMAP_EN is pulled down by default in EVM. But as per TI, (refer earlier post from Rex), it is interpreted as '1'. I have used the BMC commands given by Rex to set DDR3A_REMAP_EN to 0 and 1 and test the addressing scenarios described in the datasheet which matches with the documentation.

Inorder to understand DDR3A_REMAP_EN/GPIO16 interpretation, we can have another thread open. I guess, this is read by MCU/RBL and interpreted internally.

Rex,

Can you please throw some light on DDR3A_REMAP_EN interpretation?

Regards

Rams

0 Kjetil Østerås over 11 years ago in reply to Rex Chang

Intellectual 370 points

Hi Rex,

Providing the bmc log really helped me understand what setup I am running. Now I know that my setup is booting with DDR3A_REMAP_EN=1 so the ARM sees only the first 512M of the DDR3B. Does this mean that I must configure the mpmsrv to load the DSP ELF images that are using DDR into 0x6000 0000? And does this also mean that DSP images that are loaded by ARM are limited to only use the first 512M of memory?

0 Rex Chang over 11 years ago in reply to Kjetil Østerås

TI__Guru 50170 points

Theoretically, you may, but the Keystone-2 Linux does not configure DDR3B memory, hence it does not use DDR3B. If you take a look at the TI mpm example, it uses the last 512MB area starting at 0xa000 0000 to be used by DSP, and the size is configurable through mem_reserve of U-boot variable. Through ARM MMU and DSP MPAX configuration, the area 0xa000 0000 is mapped to the physical address (0x08 2000 0000) where it can be accessed by both ARM and DSP.

0 Kjetil Østerås over 11 years ago in reply to Rex Chang

Intellectual 370 points

Hi Rex,

Reserving the last 512MiB of DDR3A memory and expecting that reserved memory to be at location 0xa000 0000 will only be correct if the size of DDR3A is 1GiB. In my case the DDR3A is 2GiB so the last 512MiB of reserved memory will be located at logical memory address 0xe000 0000 (physical 0x08 6000 0000). So it looks like I have to adjust the dspmem setting in the linux device tree and adjust the address in the mpm configuration.

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XTCIEVMK2X Rev1.0: ARM view and DSP view of DDR3A and DDR3B