• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 102 subscribers
  • Views 7578 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UDIMM DDR3 on C665x

Ivan Pessina
Prodigy 65 points

Dear All,

No one has never used UDIMM DDR3 with C665x as per SPRABI1A?

I would be sure this is well opterating and I am not sure how to accomodate the two CLKOUT and 36 data bus with 240 pinout UDIMM.

There are rules to accomodate the C665x DDR3 bus with these UDIMM module?

If somone can reply the question, Thanks Ivan 

  • 0
    Intellectual 815 points

    Привет Иван. вот с ddr3 лично у меня вообще беда.

  • 0
    TI__Mastermind 42545 points

    Hi Ivan,

    We did use a single-rank 240pin UDIMM module on our silicon verification platform for the C665x. For single-rank DIMM modules, only DDRCLKOUT0P/N is used. We connected the DDRD0-31 to the DQ0-31 pinsand connected DDRCB0-3 to the CB0-3 pins of the UDIMM connector. All address and command pins need to be connected as well. All routing rules should be followed between the C665x and the UDIMM connector. Note that UDIMMs are designed for 64bit data bus access and you are wasting half of the memory capacity. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 65 points

    Thank You Bill,


    they are very useful info for verification!!!

    I also understood that it is not needed to connect not used DDR3 DATA (self polarisation to reference) and a mistake in the user manual, pin 1 connected to reference and not supply. 

    Ivan

  • 0 in reply to Ivan Pessina
    TI__Mastermind 42545 points

    Hi Ivan,

    You are correct that pin 1 is incorrectly labeled in the current version of the DDR3 Design Requirements Document. Pin 1 should be connected to the 0.75V reference voltage and not the DVDD15 rail. This will be fixed in the next revision.

    Regards, Bill