OMP, SRIO, NDK on c6678

Pavel1

I try to join omp-style programming, SRIO and NDK drivers in my project.

After long time I made it. I have full-working NDK and OMP. But SRIO driver works only in DIO mode. I use MCSDK SRIO driver. I adapted loopback example for my project. I saw, that SRIO exanges in DIO mode are completed between some boards.

But when I tried to use type 11 transaction in RAW mode I had fault. I had success with type 11 message transactions between boards when I used same project without OMP. But with OMP I have problem. When I try to use type 11 transaction with OMP I haven't any error in SRIO driver. I saw that host descriptor entered to queue number 672. But from queue 672 transaction is not exited.

After every SockSend call the A register (counter of queue items) from 672 queue incremented per 1. When I tried same project without OMP register A is equal 0 (queue is empty because TX transaction completed (I see it using packet counter in SRIO switch)).

My question is: whats a problem with 672 queue? may be I need to do additional initialisation is compare Loopback Example?

P.S. My sequence of initialisation is:

1. (Before OMP init) qmss_init, Memregion(Ethernet) init, Memregion (SRIO) init

2. OMP automatic init (memregion 3)

3. main

4. CPPI init

5. NDK init

6. SRIO driver init

P.P.S I tryed to use double _mfence instruction like in errata sheet: no effect.

over 11 years ago

0 Pubesh over 11 years ago

TI__Mastermind 20790 points

Hi,

Please mention the board details like TI EVM or Custom board.
Here the Queue Start Index is 672 for SRIO queues with 16 queue count.
If possible please provide a code snippet so that we can examine this issue.

0 Pavel1 over 11 years ago in reply to Pubesh

Intellectual 300 points

Thank you for your response

My code is:

1. cfg file

var Memory    = xdc.useModule('xdc.runtime.Memory');
var Log       = xdc.useModule('xdc.runtime.Log');
var Error     = xdc.useModule('xdc.runtime.Error');
var Diags     = xdc.useModule('xdc.runtime.Diags');
var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
var Startup   = xdc.useModule('xdc.runtime.Startup');
var System    = xdc.useModule('xdc.runtime.System');
//var SysStd    = xdc.useModule('xdc.runtime.SysStd');
var Main      = xdc.useModule("xdc.runtime.Main");

//System.SupportProxy = SysStd;

var SysMin = xdc.useModule("xdc.runtime.SysMin");
System.SupportProxy = SysMin;
SysMin.bufSize = 0x8000;


/* Load and configure SYSBIOS packages */
var BIOS      = xdc.useModule('ti.sysbios.BIOS');
var Task      = xdc.useModule('ti.sysbios.knl.Task');
var Clock     = xdc.useModule('ti.sysbios.knl.Clock');
var Mailbox   = xdc.useModule('ti.sysbios.knl.Mailbox'); 
var Hwi       = xdc.useModule('ti.sysbios.hal.Hwi');
var Ecm       = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
var BiosCache = xdc.useModule('ti.sysbios.hal.Cache');
var HeapBuf   = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var HeapMem   = xdc.useModule('ti.sysbios.heaps.HeapMem');
var Exc       = xdc.useModule('ti.sysbios.family.c64p.Exception');
var Cache     = xdc.useModule('ti.sysbios.family.c66.Cache');
var CPINTC  = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');

BIOS.taskEnabled = true;
Task.common$.namedInstance = true;

/*
 * Enable Event Groups here and registering of ISR for specific GEM INTC is done
 * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
 */

Ecm.eventGroupHwiNum[0] = 7;
Ecm.eventGroupHwiNum[1] = 8;
Ecm.eventGroupHwiNum[2] = 9;
Ecm.eventGroupHwiNum[3] = 10;

/* Create a Heap. */
var heapMemParams = new HeapMem.Params();
heapMemParams.size = 0x8000000;
heapMemParams.sectionName = "ddr_heap";
Program.global.ddr_heap = HeapMem.create(heapMemParams);

/* Load and configure NDK */
var Global = xdc.useModule('ti.ndk.config.Global');

/* 
** This allows the heart beat (poll function) to be created but does not generate the stack threads 
**
** Look in the cdoc (help files) to see what CfgAddEntry items can be configured. We tell it NOT
** to create any stack threads (services) as we configure those ourselves in our Main Task
** thread.
*/  
Global.enableCodeGeneration = false;


/* Load the PDK packages */
var Csl  = xdc.useModule('ti.csl.Settings');
var Pa   = xdc.useModule('ti.drv.pa.Settings');
var Cppi = xdc.loadPackage('ti.drv.cppi');     
var Qmss = xdc.loadPackage('ti.drv.qmss');

/* Load the Platform/NDK Transport packages */
var PlatformLib  = xdc.loadPackage('ti.platform.evmc6678l');
var NdkTransport = xdc.loadPackage('ti.transport.ndk');

/* Use more efficient Notify driver */
var Notify        = xdc.module('ti.sdo.ipc.Notify');
Notify.SetupProxy = xdc.module('ti.sdo.ipc.family.c647x.NotifyCircSetup');

/* Use more efficient MessageQ transport */
var MessageQ = xdc.module('ti.sdo.ipc.MessageQ');
MessageQ.SetupTransportProxy = 
        xdc.useModule('ti.sdo.ipc.transports.TransportShmNotifySetup');

Startup.firstFxns.$add('&lld_init');


var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');

 

/* Load OpenMP module */
var OpenMP = xdc.useModule('ti.omp.utils.OpenMP');
OpenMP.stackSize = 0x4000;
OpenMP.setNumProcessors(2);
OpenMP.qmssInit = false;
OpenMP.ipcHeapSize = 0x30000;
OpenMP.qmssMemRegion = -1;
OpenMP.qmssStartIndex = 0;
OpenMP.qmssDestQueueNum = -1;
OpenMP.stackRegionId = -1;
OpenMP.internalOsal = true;
OpenMP.cppiHwSem = 3;
OpenMP.qmssHwSem = 4;
OpenMP.mpaxIndex = 3;
OpenMP.enableMemoryConsistency = false;

// Configure HeapOMP

// HeapOMP created in ti/omp/common.cfg.xs



var HeapOMP = xdc.useModule('ti.omp.utils.HeapOMP');
HeapOMP.sharedRegionId = 2;
HeapOMP.localHeapSize  = 0x20000;
HeapOMP.sharedHeapSize = 0x1000000;

// Specify the Shared Region

SharedRegion.setEntryMeta( HeapOMP.sharedRegionId,
                           {   base: 0x90000000,
                               len:  HeapOMP.sharedHeapSize,
                               ownerProcId: 0,
                               cacheLineSize: 0,
                               cacheEnable: false,
                               createHeap: true,
                               isValid: true,
                               name: "sr2-ddr3",
                           }
);

//

// Setup HeapOMP

//

// Initialize HeapMem parameters
var HeapOMP      = xdc.useModule('ti.omp.utils.HeapOMP');
var HeapMem      = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
heapMemParams.size = HeapOMP.localHeapSize;

// Create a HeapOMP instance
var heapOmpParams = new HeapOMP.Params();
heapOmpParams.localHeap = HeapMem.create(heapMemParams)
heapOmpParams.sRegionId = HeapOMP.sharedRegionId;

// Setup defaultHeapInstance to a HeapOMP instance

var Memory       = xdc.useModule('xdc.runtime.Memory');
if (Memory.defaultHeapInstance)
    Program.$logWarning("Memory.defaultHeapInstance already set!", this);

Memory.defaultHeapInstance = HeapOMP.create(heapOmpParams)

Task.defaultStackSize = 0x4000;
//BIOS.heapSize = 0x50000;


Program.sectMap[".cio"]              = {loadSegment: "L2SRAM", loadAlign:8};
Program.sectMap[".args"]             = {loadSegment: "L2SRAM", loadAlign:8};
Program.sectMap[".cppi"]             = {loadSegment: "MSMCSRAM", loadAlign:16};
Program.sectMap[".qmss"]             = {loadSegment: "MSMCSRAM", loadAlign:16};
Program.sectMap[".nimu_eth_ll2"]     = {loadSegment: "MSMCSRAM", loadAlign:16};
Program.sectMap[".far:NDK_PACKETMEM"]= {loadSegment: "MSMCSRAM", loadAlign: 128};
Program.sectMap[".far:NDK_OBJMEM"]   = {loadSegment: "L2SRAM", loadAlign: 16};
Program.sectMap[".far:WEBDATA"]      = {loadSegment: "DDR3", loadAlign: 8};
Program.sectMap[".resmgr_memregion"] = {loadSegment: "MSMCSRAM", loadAlign:128};
Program.sectMap[".resmgr_handles"]   = {loadSegment: "MSMCSRAM", loadAlign:16};
Program.sectMap[".resmgr_pa"]        = {loadSegment: "MSMCSRAM", loadAlign:8};
Program.sectMap[".srioSharedMem"]        = {loadSegment: "MSMCSRAM", loadAlign:8};

Program.sectMap["ddr_heap"]          = "DDR3";
Program.sectMap[".plt"]              = "MSMCSRAM";
Program.sectMap["platform_lib"]      = "MSMCSRAM";
Program.sectMap[".text"]             = "MSMCSRAM";
Program.sectMap[".far:NDK_MMBUFFER1"]= "MSMCSRAM";

Program.sectMap[".fftcoef"]             = "MSMCSRAM";
Program.sectMap[".init_code"]= "MSMCSRAM";

Program.sectMap["ddr"] = new Program.SectionSpec();
Program.sectMap["ddr"].loadSegment = "DDR3_NOCACHE";
Program.sectMap[".threadprivate"] = new Program.SectionSpec();
Program.sectMap[".threadprivate"].loadSegment = "L2SRAM";

var Cache        = xdc.useModule('ti.sysbios.family.c66.Cache');

// Do not cache DDR - Shared region 2 in OpenMP.xs is marked as non-cacheable
// These 2 settings need to be in sync!
Cache.setMarMeta(0x90000000, 0x10000000, 0);
//Cache.setMarMeta(0x80000000, 0x20000000, 0);



/*BIOS.libType = BIOS.LibType_Debug;*/

Exc.enableExternalMPC = false;

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

init QMSS

-------------------------------------------------

void lld_init(void)
{
    QMSS_CFG_T      qmss_cfg;
    int ret=0;

   /*  Initialize QMSS */
    if (platform_get_coreid() == 0)
    {
        qmss_cfg.master_core        = 1;
    }
    else
    {
        return;
    }



    if(res_mgr_init_qmss_global (MAX_NUM_DESC_OTHER + MAX_NUM_DESC)!=0)
    	{

    	printf ("Failed system init\n");
    	return;
    	}
    else
    	{

    	printf ("SystemInit is complete\n");
    	}
    InitDSPSystem();


    if(ConfigQMSS()!=0)
      	{
          printf ("Failed to initialize the QMSS subsystem \n");
          return;
      	}
      else
      	{
      	printf ("QMSS successfully initialized \n");
      	}

    return;
}


/* Memory allocated for the descriptors. This is 16 bit aligned. */
#pragma DATA_SECTION(host_region_eth_desc, ".resmgr_memregion");
#pragma DATA_ALIGN (host_region_eth_desc, 128)
uint8_t             host_region_eth_desc[NUM_DESC_ETH * MAX_DESC_SIZE_ETH];


/* Memory allocated for the descriptors. This is 16 bit aligned. */
#pragma DATA_SECTION(host_region_srio_desc, ".resmgr_memregion");
#pragma DATA_ALIGN (host_region_srio_desc, 128)
uint8_t             host_region_srio_desc[2*NUM_DESC_SRIO * MAX_DESC_SIZE_SRIO];


int32_t ConfigQMSS()
	{

	    int32_t                     result;
	    Qmss_MemRegInfo             memCfg;
	    Qmss_InitCfg                qmssInitConfig;
	    Cppi_DescCfg                cppiDescCfg;
	    uint32_t                    numAllocated;


	        /* Start the QMSS. */

	    /* Setup the descriptor memory regions.
	     *
	     * The Descriptor base addresses MUST be global addresses and
	     * all memory regions MUST be setup in ascending order of the
	     * descriptor base addresses.
	     */

	   /*     memset (gHostDesc, 0, p_qmss_cfg->desc_size * p_qmss_cfg->max_num_desc);
	        memCfg.descBase             =   (uint32_t *) Convert_CoreLocal2GlobalAddr ((uint32_t) gHostDesc);
	        memCfg.descSize             =   p_qmss_cfg->desc_size;
	        memCfg.descNum              =   p_qmss_cfg->max_num_desc;
	        memCfg.manageDescFlag       =   Qmss_ManageDesc_MANAGE_DESCRIPTOR;
	        memCfg.memRegion            =   p_qmss_cfg->mem_region;
	        memCfg.startIndex           =   0;

*/

	    /* Initialize and setup CPSW Host Descriptors required for example */
	    memset ((void *)&host_region_eth_desc, 0, sizeof(host_region_eth_desc));
	    memCfg.descBase             =   (uint32_t *) Convert_CoreLocal2GlobalAddr ((uint32_t) host_region_eth_desc);
	    memCfg.descSize             =   MAX_DESC_SIZE_ETH;
	    memCfg.descNum              =   NUM_DESC_ETH;
	    memCfg.manageDescFlag       =   Qmss_ManageDesc_MANAGE_DESCRIPTOR;
	    memCfg.memRegion            =   Qmss_MemRegion_MEMORY_REGION_NOT_SPECIFIED;
	    memCfg.startIndex           =   0;

	    /* Insert Host Descriptor memory region */
	    result = Qmss_insertMemoryRegion(&memCfg);
	    if (result == QMSS_MEMREGION_ALREADY_INITIALIZED)
	    {
	    	printf ("Memory Region %d already Initialized \n", memCfg.memRegion);
	    }
	    else if (result < QMSS_SOK)
	    {
	    	printf ("Error: Inserting memory region %d, Error code : %d\n", memCfg.memRegion, result);
	        return -1;
	    }
		else
			{
			printf ("Memory Region %d Initialized \n", result);
			}

	    DriverDSPstruct.memRegionEth=(Qmss_MemRegion)result;


	    // Create Ethernet  MemRegion!!!

	    /* Initialize all the descriptors we just allocated on the
	     * memory region above. Setup the descriptors with some well
	     * known values before we use them for data transfers.
	     */
	    memset (&cppiDescCfg, 0, sizeof (cppiDescCfg));
	    cppiDescCfg.memRegion       =   DriverDSPstruct.memRegionEth;
	    cppiDescCfg.descNum         =   NUM_DESC_ETH;
	    cppiDescCfg.destQueueNum    =   QMSS_PARAM_NOT_SPECIFIED;
	    cppiDescCfg.queueType       =   Qmss_QueueType_GENERAL_PURPOSE_QUEUE;
	    cppiDescCfg.initDesc        =   Cppi_InitDesc_INIT_DESCRIPTOR;
	    cppiDescCfg.descType        =   Cppi_DescType_HOST;

	    /* By default:
	     *      (1) Return descriptors to tail of queue
	     *      (2) Always return entire packet to this free queue
	     *      (3) Set that PS Data is always present in start of SOP buffer
	     *      (4) Configure free q num < 4K, hence qMgr = 0
	     *      (5) Recycle back to the same Free queue by default.
	     */
	    cppiDescCfg.returnPushPolicy            =   Qmss_Location_TAIL;
	    cppiDescCfg.cfg.host.returnPolicy       =   Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET;
	    cppiDescCfg.cfg.host.psLocation         =   Cppi_PSLoc_PS_IN_DESC;
	    cppiDescCfg.returnQueue.qMgr            =   0;
	    cppiDescCfg.returnQueue.qNum            =   QMSS_PARAM_NOT_SPECIFIED;
	    cppiDescCfg.epibPresent                 =   Cppi_EPIB_EPIB_PRESENT;

	    /* Initialize the descriptors, create a free queue and push descriptors to a global free queue */
	    if ((gGlobalFreeQHnd = Cppi_initDescriptor (&cppiDescCfg, &numAllocated)) <= 0)
	    {
	    	printf ("Error Initializing Free Descriptors, Error: %d \n", gGlobalFreeQHnd);
	        return -1;
	    }

	    if (numAllocated != cppiDescCfg.descNum)  {
	    	printf ("function Init_Qmss: expected %d descriptors to be initialized, only %d are initialized\n", cppiDescCfg.descNum, numAllocated);
	      return (-1);
	    }


	    // init SRIO region


	    	memset ((void *)&host_region_srio_desc, 0, sizeof(host_region_srio_desc));
		// Memory Region Configuration
	    	memCfg.descBase         = (uint32_t *)Convert_CoreLocal2GlobalAddr((uint32_t)host_region_srio_desc);
	    	memCfg.descSize         = MAX_DESC_SIZE_SRIO;
	    	memCfg.descNum          = 2*NUM_DESC_SRIO;
	    	memCfg.manageDescFlag   = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
	    	memCfg.memRegion        = Qmss_MemRegion_MEMORY_REGION_NOT_SPECIFIED;
		    memCfg.startIndex           =  0;

			// Initialize and inset the memory region.
			result = Qmss_insertMemoryRegion (&memCfg);
		    if (result == QMSS_MEMREGION_ALREADY_INITIALIZED)
		    {
		    	printf ("Memory Region %d already Initialized \n", memCfg.memRegion);
		    }
		    else if (result < QMSS_SOK)
			{
				printf ("Error inserting memory SRIO region: %d\n", result);
				return -1;
			}
			else
				{
				printf ("Memory Region %d Initialized \n", result);
				}


		DriverDSPstruct.memRegionSRIO=(Qmss_MemRegion)result;

	    /* Queue Manager Initialization Done */
	    return 0;


	}

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

init CPPI

init SRIO driver

--------------------------------------------

// first line in main function
int InitCPPI()
	{
	int result;
	if (CSL_chipReadReg (CSL_CHIP_DNUM)==0)
		{
		/* Initialize CPPI LLD */
		result = Cppi_init (&cppiGblCfgParams[0]);
		if (result != CPPI_SOK)
			{
			printf ("Error initializing CPPI LLD, Error code : %d\n", result);
			return -1;
			}
		else
    		{
			printf ("Init CPPI completed\n");
    		}
		}
	return 0;
	}

///////////////////////////////////////
// in main function
void CommonSRIOConfig()
	{
	/* Power on SRIO peripheral before using it */
	if (enable_srio () < 0)
	{
		printf ("Error: SRIO PSC Initialization Failed\n");
		return;
	}
	else
		{
		printf ("SRIO PSC is init\n");
		}

    if (Osal_dataBufferInitMemory(SRIO_MAX_MTU) < 0)
	{
	    printf ("Error: Unable to initialize the OSAL. \n");
	    return;
    }

	/* Device Specific SRIO Initializations: This should always be called before
	 * initializing the SRIO Driver. */
	if (SrioDevice_init () < 0)
		{
    	printf ("Error: SrioDevice_init\n");

		return;
		}
	else
		{
		printf ("SrioDevice_init is complete\n");
		}

	/* Initialize the SRIO Driver */
	if (Srio_init () < 0)
		{
    	printf ("Error: Srio_init\n");

		return;
		}
	else
		{
		printf ("Srio_init is complete\n");
		}
   
    /* Clear Errors*/
    clearSrioStatusErrors ();



    /* Create the Application Managed Configuration. */
    if (setupSRIOAppConfig() == -1)
    	{
    	printf ("Error: setupSRIOAppConfig\n");

        return;
    	}
    else
    	{
    	printf ("setupSRIOAppConfig is complete\n");
    	}

    ///////////
  	}
///////////////////
/* XDC Includes. */
#include <xdc/runtime/System.h>
#include <stdio.h>

/* CSL SRIO Functional Layer */
#include <ti/csl/csl_srio.h>
#include <ti/csl/csl_srioAux.h>
#include <ti/csl/csl_srioAuxPhyLayer.h>

/* SRIO Driver Includes. */
#include <ti/drv/srio/srio_types.h>
#include <ti/drv/srio/include/listlib.h>
#include <ti/drv/srio/srio_drv.h>

/* Application Include Files */
#include "srio_laneconfig.h"

/* CSL BootCfg Module */
#include <ti/csl/csl_bootcfg.h>
#include <ti/csl/csl_bootcfgAux.h>

/* CSL PSC Module */
#include <ti/csl/csl_pscAux.h>

/* CSL Chip Functional Layer */
#include <ti/csl/csl_chip.h>

/* QMSS Include */
#include <ti/drv/qmss/qmss_drv.h>

/* Producer-Consumer Include Files. */
#include "../dsp_system/benchmarking.h"
#include "../dsp_system/dsp_system.h"



extern _DriverDSPstruct DriverDSPstruct;

/**********************************************************************
 ************************* LOCAL Definitions **************************
 **********************************************************************/

/* These are the GARBAGE queues which are used by the TXU to dump the 
 * descriptor if there is an error instead of recycling the descriptor
 * to the free queue. */
#define GARBAGE_LEN_QUEUE		    1905
#define GARBAGE_TOUT_QUEUE		    1906
#define GARBAGE_RETRY_QUEUE		    1907
#define GARBAGE_TRANS_ERR_QUEUE	    1908
#define GARBAGE_PROG_QUEUE		    1909
#define GARBAGE_SSIZE_QUEUE		    1910

/* SRIO Device Information
 * - 16 bit Device Identifier.
 * - 8 bit Device Identifier.
 * - Vendor Identifier. 
 * - Device Revision. */
#define DEVICE_VENDOR_ID            0x30
#define DEVICE_DEVICE_ID            0x9D
#define DEVICE_REVISION             0x0

/* SRIO Assembly Information
 * - Assembly Identifier
 * - Assembly Vendor Identifier. 
 * - Assembly Device Revision. 
 * - Assembly Extension Features */
#define DEVICE_ASSEMBLY_ID          0x0
#define DEVICE_ASSEMBLY_VENDOR_ID   0x30
#define DEVICE_ASSEMBLY_REVISION    0x0
#define DEVICE_ASSEMBLY_INFO        0x0100

/**********************************************************************
 ************************* Extern Definitions *************************
 **********************************************************************/


/* Ref clock enum is defined in srio_laneconfig.h */
#if defined(_TCI6614_Atrenta_DSP1_H_)
  /* tci6614 */
srioRefClockMhz_e srio_refClockMhz = srio_ref_clock_312p50Mhz;
#elif defined(_C6657_Atrenta_DSP1_H_)
  /* c6657 */
srioRefClockMhz_e srio_refClockMhz = srio_ref_clock_250p00Mhz;
#elif defined(_C6678_Atrenta_DSP1_H_) || defined(_TCI6608_Atrenta_DSP1_H_)
  /* c6678, tci6608 */
srioRefClockMhz_e srio_refClockMhz = srio_ref_clock_312p50Mhz;
#elif defined(_C6670_Atrenta_DSP1_H_) || defined(_TCI6616_Atrenta_DSP1_H_) || defined(_TCI6618_Atrenta_DSP1_H_)
  /* c6670, tci6616, tci6618 */
srioRefClockMhz_e srio_refClockMhz = srio_ref_clock_250p00Mhz;
#else
/* The cslr_device.h doesn't provide a known device identifier define */
#error Unknown device identified
#endif

/**********************************************************************
 *********************** DEVICE SRIO FUNCTIONS ***********************
 **********************************************************************/

/** @addtogroup SRIO_DEVICE_API
 @{ */

/**
 *  @b Description
 *  @n
 *      The function provides the initialization sequence for the SRIO IP
 *      block. This can be modified by customers for their application and
 *      configuration.
 *
 *  @retval
 *      Success     -   0
 *  @retval
 *      Error       -   <0
 */
int32_t SrioDevice_init (void)
{
    CSL_SrioHandle      hSrio;
	int32_t             i;
    SRIO_PE_FEATURES    peFeatures;
    SRIO_OP_CAR         opCar;
    Qmss_QueueHnd       queueHnd;
    uint8_t             isAllocated;
    uint32_t            gargbageQueue[] = { GARBAGE_LEN_QUEUE,  GARBAGE_TOUT_QUEUE,
                                            GARBAGE_RETRY_QUEUE,GARBAGE_TRANS_ERR_QUEUE,
                                            GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE };
    uint32_t			srioIDMask = (DriverDSPstruct.srio_isDeviceID16Bit ? 0xFFFF : 0xFF);
    uint32_t			srio_primary_ID = DriverDSPstruct.PrimaryDeviceID;
    uint32_t			srio_secondary_ID = DriverDSPstruct.SecondaryDeviceID;

	Uint8 pri;


    /* Set primary port ID based on whether going board to board and the
     * initialization core number */



#ifndef SIMULATOR_SUPPORT
    /* Disable SRIO reset isolation */
    if (CSL_PSC_isModuleResetIsolationEnabled(CSL_PSC_LPSC_SRIO))
    	CSL_PSC_disableModuleResetIsolation(CSL_PSC_LPSC_SRIO);

    /* Reset SRIO module and wait for the reset to complete */
    CSL_PSC_setModuleLocalReset (CSL_PSC_LPSC_SRIO,PSC_MDLRST_ASSERTED);
    CSL_PSC_setModuleNextState (CSL_PSC_LPSC_SRIO,PSC_MODSTATE_ENABLE);
    printf ("Debug: Waiting for module reset...\n");
    while (!CSL_PSC_isModuleResetDone(CSL_PSC_LPSC_SRIO));
    printf ("Debug: Waiting for module local reset...\n");
    while (!CSL_PSC_isModuleLocalResetDone (CSL_PSC_LPSC_SRIO));
#endif

    /* Get the CSL SRIO Handle. */
    hSrio = CSL_SRIO_Open (0);
    if (hSrio == NULL)
    	{
    	printf ("Error: hSrio == NULL\n");
        return -1;
    	}

    /* Enable reception of packets */
	hSrio->RIO_PCR = (hSrio->RIO_PCR & 0x7) | CSL_SRIO_RIO_PCR_RESTORE_MASK;

    /* Disable the SRIO Global block */
	CSL_SRIO_GlobalDisable (hSrio);

	/* Disable each of the individual SRIO blocks. */
	for(i = 0; i <= 9; i++)
		CSL_SRIO_DisableBlock (hSrio, i);

	/* Set boot complete to be 0; we are not done with the initialization. */
	CSL_SRIO_SetBootComplete (hSrio, 0);

    /* Set the sRIO shadow registers for 9/3/2/2 */
    CSL_SRIO_SetLSUShadowRegs (hSrio,0x19,0x19);

	/* Now enable the SRIO block and all the individual blocks also. */
	CSL_SRIO_GlobalEnable (hSrio);
	for (i = 0; i <= 9; i++)
		CSL_SRIO_EnableBlock (hSrio,i);

/*	if (testControl.srio_isLoopbackMode)
	{
		// Configure SRIO to operate in Loopback mode.
		CSL_SRIO_SetLoopbackMode (hSrio,0);
		CSL_SRIO_SetLoopbackMode (hSrio,1);
		CSL_SRIO_SetLoopbackMode (hSrio,2);
		CSL_SRIO_SetLoopbackMode (hSrio,3);
	}
	else
	{*/
		/* Configure SRIO to operate in Normal mode. */
		CSL_SRIO_SetNormalMode (hSrio,0);
		CSL_SRIO_SetNormalMode (hSrio,1);
		CSL_SRIO_SetNormalMode (hSrio,2);
		CSL_SRIO_SetNormalMode (hSrio,3);
	//}

	/* Enable Automatic Priority Promotion of response packets. */
	CSL_SRIO_EnableAutomaticPriorityPromotion (hSrio);

	/* Set the SRIO Prescalar select to operate in the range of 44.7 to 89.5 */
	CSL_SRIO_SetPrescalarSelect (hSrio, 0);

    /* Unlock the Boot Configuration Kicker */
    CSL_BootCfgUnlockKicker ();

	if (setEnableSrioPllRxTx(hSrio, srio_refClockMhz, DriverDSPstruct.srio_laneSpeedGbps, 0) < 0)
		{
    	printf ("Error: setEnableSrioPllRxTx\n");
		return -1;

		}

    /* Loop around until the SERDES PLL is locked. */
    while (1)
    {
        uint32_t    status;

        /* Get the SRIO SERDES Status */
        CSL_BootCfgGetSRIOSERDESStatus (&status);
        if (status & 0x1)
            break;
    }

    /* Clear the LSU pending interrupts. */
    CSL_SRIO_ClearLSUPendingInterrupt (hSrio, 0xFFFFFFFF, 0xFFFFFFFF);

    /* Set the Device Information */
    CSL_SRIO_SetDeviceInfo (hSrio, DEVICE_DEVICE_ID, DEVICE_VENDOR_ID, DEVICE_REVISION);

    /* Set the Assembly Information */
    CSL_SRIO_SetAssemblyInfo (hSrio, DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID,
                             DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);

	/* Configure the processing element features*/
	peFeatures.isBridge                          = 0;
	peFeatures.isEndpoint                        = 0;
	peFeatures.isProcessor                       = 1;
	peFeatures.isSwitch                          = 0;
	peFeatures.isMultiport                       = 0;
	peFeatures.isFlowArbiterationSupported       = 0;
	peFeatures.isMulticastSupported              = 0;
	peFeatures.isExtendedRouteConfigSupported    = 0;
	peFeatures.isStandardRouteConfigSupported    = 1;
	peFeatures.isFlowControlSupported            = 1;
	peFeatures.isCRFSupported                    = 0;
	peFeatures.isCTLSSupported                   = 1;
	peFeatures.isExtendedFeaturePtrValid         = 1;
	peFeatures.numAddressBitSupported            = 1;
	CSL_SRIO_SetProcessingElementFeatures (hSrio, &peFeatures);

	/* Configure the source operation CAR */
	memset ((void *) &opCar, 0, sizeof (opCar));
	opCar.portWriteOperationSupport = 1;
	opCar.atomicClearSupport        = 1;
	opCar.atomicSetSupport          = 1;
	opCar.atomicDecSupport          = 1;
	opCar.atomicIncSupport          = 1;
	opCar.atomicTestSwapSupport     = 1;
	opCar.doorbellSupport           = 1;
	opCar.dataMessageSupport        = 1;
	opCar.writeResponseSupport      = 1;
	opCar.streamWriteSupport        = 1;
	opCar.writeSupport              = 1;
	opCar.readSupport               = 1;
	opCar.dataStreamingSupport      = 1;
	CSL_SRIO_SetSourceOperationCAR (hSrio, &opCar);

	/* Configure the destination operation CAR */
	memset ((void *) &opCar, 0, sizeof (opCar));
	opCar.portWriteOperationSupport  = 1;
	opCar.doorbellSupport            = 1;
	opCar.dataMessageSupport         = 1;
	opCar.writeResponseSupport       = 1;
	opCar.streamWriteSupport         = 1;
	opCar.writeSupport               = 1;
	opCar.readSupport                = 1;
	CSL_SRIO_SetDestOperationCAR (hSrio, &opCar);

	/* Set the 16 bit and 8 bit identifier for the SRIO Device. */
	CSL_SRIO_SetDeviceIDCSR (hSrio, DriverDSPstruct.Dest_ID1_8BIT, DriverDSPstruct.Dest_ID1_16BIT);

    /* Enable TLM Base Routing Information for Maintainance Requests & ensure that
     * the BRR's can be used by all the ports. */
    CSL_SRIO_SetTLMPortBaseRoutingInfo (hSrio, 0, 1, 1, 1, 0);
    /* Only add additional route if doing core to core on the same board */
   // if (!testControl.srio_isBoardToBoard)
	//CSL_SRIO_SetTLMPortBaseRoutingInfo (hSrio, 0, 2, 1, 1, 0);

    /* Configure the Base Routing Register to ensure that all packets matching the 
     * Device Identifier & the Secondary Device Id are admitted. */
    CSL_SRIO_SetTLMPortBaseRoutingPatternMatch (hSrio, 0, 1, srio_primary_ID, srioIDMask);
    /* Only add additional route if doing core to core on the same board */
    //if (!testControl.srio_isBoardToBoard)
	 //  CSL_SRIO_SetTLMPortBaseRoutingPatternMatch (hSrio, 0, 2, srio_secondary_ID, srioIDMask);

    /* We need to open the Garbage collection queues in the QMSS. This is done to ensure that 
     * these queues are not opened by another system entity. */
    for (i = 0; i < 6; i++)
    {
        /* Open the Garabage queues */
        queueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, gargbageQueue[i], &isAllocated);
        if (queueHnd < 0)
			{
        	printf ("Error: Qmss_queueOpen\n");
        	return -1;
			}


        /* Make sure the queue has not been opened already; we dont the queues to be shared by some other
         * entity in the system. */
        if (isAllocated > 1)
        	{
        	printf ("Error: isAllocated  = %d\n",gargbageQueue[i]);
        	return -1;
        	}
        else
        	{
        	printf ("Successful isAllocated = %d\n",gargbageQueue[i]);
        	}
    }

    /* Set the Transmit Garbage Collection Information. */
    CSL_SRIO_SetTxGarbageCollectionInfo (hSrio, GARBAGE_LEN_QUEUE, GARBAGE_TOUT_QUEUE, 
                                         GARBAGE_RETRY_QUEUE, GARBAGE_TRANS_ERR_QUEUE, 
                                         GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE);

    /* Set the Host Device Identifier. */
    CSL_SRIO_SetHostDeviceID (hSrio, DEVICE_DEVICE_ID);

    /* Configure the component tag CSR */
    CSL_SRIO_SetCompTagCSR (hSrio, 0x00000000);

	/* Configure the PLM for all the ports. */
	for (i = 0; i < 4; i++)
	{
		/* Set the PLM Port Silence Timer. */
		CSL_SRIO_SetPLMPortSilenceTimer (hSrio, i, 0x2);

		/* TODO: We need to ensure that the Port 0 is configured to support both
		 * the 2x and 4x modes. The Port Width field is read only. So here we simply
		 * ensure that the Input and Output ports are enabled. */
		CSL_SRIO_EnableInputPort (hSrio, i);
		CSL_SRIO_EnableOutputPort (hSrio, i);

		/* Set the PLM Port Discovery Timer. */
		CSL_SRIO_SetPLMPortDiscoveryTimer (hSrio, i, 0x2);

		/* Reset the Port Write Reception capture. */
		CSL_SRIO_SetPortWriteReceptionCapture (hSrio, i, 0x0);
	}

	/* Set the Port link timeout CSR */
	// CSL_SRIO_SetPortLinkTimeoutCSR (hSrio, 0x000FFF);
	CSL_SRIO_SetPortLinkTimeoutCSR (hSrio, 0xFF0FFF);
	CSL_SRIO_SetPortResponseTimeoutCSR (hSrio, 0xFF0FFF);

	/* Set the Port General CSR: Only executing as Master Enable */
	CSL_SRIO_SetPortGeneralCSR (hSrio, 0, 1, 0);

	/* Clear the sticky register bits. */
	CSL_SRIO_SetLLMResetControl (hSrio, 1);

	/* Set the device id to be 0 for the Maintenance Port-Write operation
	 * to report errors to a system host. */
	CSL_SRIO_SetPortWriteDeviceId (hSrio, 0x0, 0x0, 0x0);

    /* Set the Data Streaming MTU */
    CSL_SRIO_SetDataStreamingMTU (hSrio, 64);

	/* Configure the path mode for the ports. */
	if (setSrioLanes(hSrio, DriverDSPstruct.srio_lanesMode) < 0)
		{
    	printf ("Error: setSrioLanes\n");
    	return -1;
		}


	/* Set the LLM Port IP Prescalar. */
	//CSL_SRIO_SetLLMPortIPPrescalar (hSrio, 0x21);
	CSL_SRIO_SetLLMPortIPPrescalar (hSrio, 0x1F);

	/* Configure the ingress watermarks */
	for (i = 0; i < 4; i++)
	{
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 0, 0x24, 0x24);
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 1, 0x1B, 0x1B);
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 2, 0x12, 0x12);
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 3, 0x9, 0x9);
	}

    /* Disable interrupt pacing for all interrupt destinations. */
    for (i = 0; i < 24; i++)
        CSL_SRIO_DisableInterruptPacing (hSrio, i);

	/* Set all the queues 0 to operate at the same priority level and to send packets onto Port 0 */
    for (i =0 ; i < 16; i++)
    	CSL_SRIO_SetTxQueueSchedInfo (hSrio, i, 0, 0);

#if 0
    /* Set the Doorbell route to determine which routing table is to be used 
     * This configuration implies that the Interrupt Routing Table is configured as 
     * follows:-
     *  Interrupt Destination 0 - INTDST 16 
     *  Interrupt Destination 1 - INTDST 17 
     *  Interrupt Destination 2 - INTDST 18
     *  Interrupt Destination 3 - INTDST 19 */
    CSL_SRIO_SetDoorbellRoute (hSrio, 0);
#else
    /* Set the Doorbell route to determine which routing table is to be used 
     * This configuration implies that the Interrupt Routing Table is configured as 
     * follows:-
     *  Interrupt Destination 0 - INTDST 0
     *  Interrupt Destination 1 - INTDST 1
     *  Interrupt Destination 2 - INTDST 2
     *  Interrupt Destination 3 - INTDST 3 */
   	CSL_SRIO_SetDoorbellRoute (hSrio, 1);
#endif    

    /* Route the Doorbell interrupts. 
     *  Doorbell Register 0 - All 16 Doorbits are routed to Interrupt Destination 0. 
     *  Doorbell Register 1 - All 16 Doorbits are routed to Interrupt Destination 1. 
     *  Doorbell Register 2 - All 16 Doorbits are routed to Interrupt Destination 2. 
     *  Doorbell Register 3 - All 16 Doorbits are routed to Interrupt Destination 3. */
    for (i = 0; i < 16; i++)
    {
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 0, i, 0);
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 1, i, 1);
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 2, i, 2);
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 3, i, 3);
    }

	/* Enable the peripheral. */
	CSL_SRIO_EnablePeripheral (hSrio);

    /* Configuration has been completed. */
    CSL_SRIO_SetBootComplete (hSrio, 1);

#ifndef SIMULATOR_SUPPORT
    /* Check Ports and make sure they are operational. */
	if (waitAllSrioPortsOperational(hSrio, DriverDSPstruct.srio_lanesMode) < 0)
		{
		printf ("Error: setSrioLanes\n");
		return -1;
		}
#endif

    if (displaySrioLanesStatus(hSrio) < 0)
		{
    	printf ("Error: setSrioLanes\n");
    	return -1;
		}


    	CSL_SRIO_GetTransactionPriority(hSrio,&pri);







    /* Initialization has been completed. */
    return 0;
}

/**
@}
*///////

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

Srio Driver config in DRIVER management mode

------------------------------------------------------

/* Memory used for the accumulator list. */
#pragma DATA_ALIGN (gHiPriAccumListSRIO, 16)
uint32_t            gHiPriAccumListSRIO[64];



/* There is a sRIO related issue in the CDMA where if the payload fills the buffer exactly
 * (such as a 4KB message into a 4KB buffer) it will chain a second buffer that will not
 * contain any data. The work around is to add an extra byte beyond the maximum payload
 * size expected to the receive buffer size to avoid an exact fill situation. */
#define RX_BUFFER_BYTES_ADJUSTMENT	1


/**
 *  @b Description
 *  @n
 *      The function initializes and setups the SRIO Driver configuration
 *      to operate in application based mode.
 *
 *  @retval
 *      Success     -   0
 *  @retval
 *      Error       -   <0
 */
int32_t setupSRIOAppConfig ()
{
    Qmss_QueueHnd   tmpQueueHnd;
    uint32_t        numAllocated;
    uint8_t         isAllocated;
    Cppi_DescCfg    descCfg;
    uint16_t        index;
    Cppi_HostDesc*  ptrHostDesc;
    uint8_t*        ptrRxData;
    Srio_DrvConfig  drvCfg;
     Qmss_Queue      queueInfo;
 	uint32_t coreNum;
	Qmss_MemRegion memRegion;
	CSL_SrioHandle  hSrioCSL;
    int32_t             eventId;

 

    memRegion=DriverDSPstruct.memRegionSRIO;

	/* Get the core number. */
	coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);

    /* Initialize the SRIO Driver Configuration. */
    memset ((Void *)&drvCfg, 0, sizeof(Srio_DrvConfig));




    /* Setup the SRIO Driver Managed Configuration. */
      drvCfg.bAppManagedConfig = FALSE;

      /* Driver Managed: Receive Configuration */
      drvCfg.u.drvManagedCfg.bIsRxCfgValid             = 1;
      drvCfg.u.drvManagedCfg.rxCfg.rxMemRegion         = memRegion;
      drvCfg.u.drvManagedCfg.rxCfg.numRxBuffers        = 2;
      drvCfg.u.drvManagedCfg.rxCfg.rxMTU               = MESSAGE_MAX_DATA_SIZE;

      /* Accumulator Configuration. */
      {
  	    int32_t coreToQueueSelector[4];

          /* This is the table which maps the core to a specific receive queue. */
  	    coreToQueueSelector[0] = 712;
  	    coreToQueueSelector[1] = 713;
  	    coreToQueueSelector[2] = 714;
  	    coreToQueueSelector[3] = 715;

  	    /* Since we are programming the accumulator we want this queue to be a HIGH PRIORITY Queue */
    	    drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE,
    	    															     coreToQueueSelector[coreNum], &isAllocated);

  	    /*    myRxCompletionQueueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE,
  	                                                 QMSS_PARAM_NOT_SPECIFIED,
  	                                                 &isAllocated);*/
    	/* drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE,
    	    															     QMSS_PARAM_NOT_SPECIFIED, &isAllocated);*/
  		if (drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue < 0)
  		{
  			printf ("Error: Unable to open the SRIO Receive Completion Queue\n");
  			return -1;
  		}

  		/* Accumulator Configuration is VALID. */
  		//drvCfg.u.drvManagedCfg.rxCfg.bIsAccumlatorCfgValid = 1;
  		drvCfg.u.drvManagedCfg.rxCfg.bIsAccumlatorCfgValid = 1;

  		/* Accumulator Configuration. */
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.channel             = coreToQueueSelector[coreNum]-704;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.command             = Qmss_AccCmd_ENABLE_CHANNEL;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.queueEnMask         = 0;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.queMgrIndex         = coreToQueueSelector[coreNum];
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.maxPageEntries      = 2;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.timerLoadCount      = 0;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.listEntrySize       = Qmss_AccEntrySize_REG_D;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.listCountMode       = Qmss_AccCountMode_ENTRY_COUNT;
  	    drvCfg.u.drvManagedCfg.rxCfg.accCfg.multiQueueMode      = Qmss_AccQueueMode_SINGLE_QUEUE;

          /* Initialize the accumulator list memory */
          memset ((Void *)&gHiPriAccumListSRIO[0], 0, sizeof(gHiPriAccumListSRIO));
          drvCfg.u.drvManagedCfg.rxCfg.accCfg.listAddress = Convert_CoreLocal2GlobalAddr((UInt32)&gHiPriAccumListSRIO[0]);
      }

      /* Driver Managed: Transmit Configuration */
      drvCfg.u.drvManagedCfg.bIsTxCfgValid             = 1;
      drvCfg.u.drvManagedCfg.txCfg.txMemRegion         = memRegion;
      drvCfg.u.drvManagedCfg.txCfg.numTxBuffers        = 2;
      drvCfg.u.drvManagedCfg.txCfg.txMTU               = MESSAGE_MAX_DATA_SIZE;








    DriverDSPstruct.hDrvManagedSrioDrv = Srio_start (&drvCfg);
    if (DriverDSPstruct.hDrvManagedSrioDrv == NULL)
    {
        printf ("Error: Application Managed SRIO Driver failed to start\n");
        return -1;
    }


    //// config interrupts SRIO

    /* Hook up the SRIO interrupts with the core. */
    EventCombiner_dispatchPlug (49, (EventCombiner_FuncPtr)Srio_rxCompletionIsr, (UArg)DriverDSPstruct.hDrvManagedSrioDrv, TRUE);
    EventCombiner_enableEvent(49);
    /* Map the event id to hardware interrupt 9. */
      Hwi_eventMap(9, 49);

      /* Enable interrupt 9. */
      Hwi_enableInterrupt(9);
    //return 0;

	 hSrioCSL = CSL_SRIO_Open (0);
		 if (hSrioCSL == NULL)
		    	{
		        return -1;
		    	}

		     /* SRIO DIO Interrupts need to be routed from the CPINTC0 to GEM Event.
		     *  - We have configured DIO Interrupts to get routed to Interrupt Destination 0
		     *    (Refer to the CSL_SRIO_RouteLSUInterrupts API configuration in the SRIO Initialization)
		     *  - We want this System Interrupt to mapped to Host Interrupt 8 */

		    /* Disable Interrupt Pacing for INTDST0 */
		    CSL_SRIO_DisableInterruptPacing (hSrioCSL, 0);

		    /* Route LSU0 ICR0 to INTDST0 */
		    CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 0, 0);

		    /* Route LSU0 ICR1 to INTDST0 */
		    CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 1, 0);

		    /* Route LSU0 ICR2 to INTDST0 */
		    CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 2, 0);


		/* SRIO DIO: Interrupts need to be routed from the CPINTC0 to GEM Event.
		 *  - We have configured DIO Interrupts to get routed to Interrupt Destination 0
		 *    (Refer to the CSL_SRIO_SetDoorbellRoute API configuration in the SRIO Initialization)
		 *  - We want this to mapped to Host Interrupt 8
		 *
		 *  Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
		CpIntc_dispatchPlug(CSL_INTC0_INTDST0, DoorbellISR_handler, (UArg)DriverDSPstruct.hDrvManagedSrioDrv, TRUE);

		/* SRIO DIO: Configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
		CpIntc_mapSysIntToHostInt(0, CSL_INTC0_INTDST0, 8);

		/* SRIO DIO: Enable the Host Interrupt. */
		CpIntc_enableHostInt(0, 8);

		/* Enable the System Interrupt */
		CpIntc_enableSysInt(0, CSL_INTC0_INTDST0);

		/* SRIO DIO: Get the event id associated with the host interrupt. */
		eventId = CpIntc_getEventId(8);



		/* SRIO DIO: Plug the CPINTC Dispatcher. */
		EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, 8, TRUE);

       CSL_SRIO_ClearLSUPendingInterrupt (hSrioCSL, 0xFFFFFFFF, 0xFFFFFFFF);

   	/* Debug Message: */
        printf ("Debug: Doorbell ISR is init\n");
        //printf ("Debug: Accumulator List: 0x%x\n", appCfg.u.appManagedCfg.accCfg.listAddress);

    /* Configuration was successful. */
    return 0;
}

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

SRIO send function

-------------------------------------

#define SIZE_RAW_PACKET				152

Int32 SendMessageSRIOType11( _SRIO_Type11_Transfer SRIO_Type11_Transfer)
	{
	    Srio_SockHandle         srioSocket1;
	    Srio_SockBindAddrInfo   bindInfo;
	    Cppi_DescCfg            descCfg;
	    
	    UInt32                  numAllocated;
	   
	    UInt32                  allocatedLen;
	    unsigned int 			txNumBytes=0;
	    Srio_SockAddrInfo       to;
	    Srio_DrvBuffer          hDrvBuffer;




	    if (SRIO_Type11_Transfer.NumByte > SIZE_RAW_PACKET)
	    {
	        printf ("Error: Exceed possible msg len\n");
	        return -1;
	    }



	    /* Open RAW TYPE11 SRIO Socket */
	    srioSocket1 =  Srio_sockOpen (DriverDSPstruct.hDrvManagedSrioDrv, Srio_SocketType_TYPE11, TRUE);
	    if (srioSocket1 == NULL)
	    {
	        printf ("Error: Unable to open socket1\n");
	        return -1;
	    }

	    /* Populate the binding information. */
	    bindInfo.type11.tt       = SRIO_Type11_Transfer.idSize;              /* We are using 16 bit identifiers.        */
	    bindInfo.type11.id       = SRIO_Type11_Transfer.source_ID;  /* Source Identifier bound to the socket   */
	    bindInfo.type11.letter   = SRIO_Type11_Transfer.letter;                 /* Letter Identifier                       */
	    bindInfo.type11.mbox     = SRIO_Type11_Transfer.messageBox;           /* Mailbox Number                          */
	    bindInfo.type11.segMap   = 0x0;               /* Single Segment                          */

	    /* Bind the SRIO socket 1 */
	    if (Srio_sockBind (srioSocket1, &bindInfo) < 0)
	    {
	        printf ("Error: socket1 bind failed\n");
	        return -1;
	    }

	    /* Get a transmit buffer from the SRIO Driver. */
	    hDrvBuffer = Srio_allocTransmitBuffer(DriverDSPstruct.hDrvManagedSrioDrv, &txData, &allocatedLen);
	    if (hDrvBuffer == NULL)
	        return -1;

	    memcpy(txData,SRIO_Type11_Transfer.msg,SRIO_Type11_Transfer.NumByte);

	    to.type11.tt       = SRIO_Type11_Transfer.idSize;                 /* We are using 16 bit identifiers.          */
	    to.type11.id       = SRIO_Type11_Transfer.dest_ID;     /* Identifier where the packet is to be sent */
	    to.type11.letter   = SRIO_Type11_Transfer.letter;                    /* Letter Identifier                         */
	    to.type11.mbox     = SRIO_Type11_Transfer.messageBox;              /* Mailbox Number                            */

	    if (Srio_sockSend (srioSocket1, hDrvBuffer, SRIO_Type11_Transfer.NumByte, &to) < 0)
		    {
	        printf ("Error: SRIO Socket Type11 send failed\n");
	        return -1;
	    }

		    /* Close the sockets. */
		    Srio_sockClose (srioSocket1);

		    return 0;
	}

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

Sorry for big size of code but each part of it depends another part.

I repeat my question.

I use two EVM6678. They are pluged in SRIO switch board SRDP2 http://silicontkx.com/srdp2.html. For routing I use solution from FetCorp (RapidFET).

I joined OMP, NDK, SRIO in one project. I have full-working OMP and NDK. In SRIO I have full-working DIO mode (NREAD, NWRITE, Doorbells (with ISR in Event 49)). But I cannot launch Type11 transaction. In OMP-less project I can do it, but when I use Full project (with OMP), code described bellow, I see that after

Srio_sockSend

register A from 672 queue is incremened. My SRIO driver use 672 queue for TX operation (I saw it using debugger). Other 15 SRIO TX queues are empty. I think my Type 11 message is not pop from 672 queue.
Please help me to initialise Type11 exchange.
exchange

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

I found one stupid error in my code:

in function SendMessageSRIOType11

in string

memcpy(hDrvBuffer,SRIO_Type11_Transfer.msg,SRIO_Type11_Transfer.NumByte);

must be

memcpy(txData,SRIO_Type11_Transfer.msg,SRIO_Type11_Transfer.NumByte);

I corrected it error in code above.

But... I have next problem: my transmit descriptor is derected to garbace queue GARBAGE_PROG_QUEUE. Whats possible reasons of it?

0 Pavel1 over 11 years ago in reply to Pavel1

Intellectual 300 points

I found my problem!

Absolutly nessesary to make region for descriptors memory as nocachable.

And library functions like l2global isn't (in osal.c for srio too) correct if you use shared or ddr memory for your memory regions. Let's rewrite this functions like Convert_CoreLocal2GlobalAddr from platform.c (rewrite Osal_local2Global )

0 Pubesh over 11 years ago in reply to Pavel1

TI__Mastermind 20790 points

Hi,

Glad to hear, solved this issue. However this discussion of thread can helpful for future readers, If you verified this thread.

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