• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 510 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H EMIF16 address generation

RY9983
Guru 10570 points

Hello,
I am planning EMIF16 to connect FPGA.

Question)
  When C66x/ARM access EMIF16 by 32bit, lower address is always generated first. Is that right?
  If there is any cases EMIF16 generates higher address first, please let me know..
  I would like to check it on my K2HEVM.

I use EMIF16 as 16bit width.
In my examination, When I observed EMIFA[23] (which operate as 16bit address) by oscilloscope, the result is all generated lower address first.
I have checked following condition:

Best regards, RY

  • 0
    TI__Mastermind 42545 points

    Hi RY,

    I understand your question but I don't have that information. There are many ways of directing accesses to the EMIF16 and I don't think the order that the accesses occur has been documented. We have tested to be sure that all accesses requested will have the proper addressing. Since this is an asynchronous access we expect the device connected will decode the addresses and present the proper data.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 10570 points

    Bill-san,

    Thank you so much for your response.

    If C66x/ARM uses 16-bit read/write instruction, we can directory control the access order to the FPGA.
    However, we would like to use 32-bit or 64-bit read/write instruction, since this will improve throughput
    as mentioned on other post.
        http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/192245.aspx?pi303753=2

    In this case, EMIF peripheral splits 32/64-bit read/write to multiple 16-bit read/write accesses.
    On AM335x GPMC peripheral, this is similar to EMIF on K2H, user guide says the access order as follows:
        http://www.ti.com/lit/ug/spruh73j/spruh73j.pdf
            7.1.3.3.8.2.2 Access Size Adaptation and Device Width

            Each chip-select can be independently configured through the GPMC_CONFIG1_i[13-12] DEVICESIZE
    field to interface with a 16-bit wide device or an 8-bit wide device. System requests with data width greater
    than the external device data bus width are split into successive accesses according to both the external
    device data-bus width and little-endian data organization.
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

    We think that EMIF peripheral on K2H has similar rules.
    If we can assume such rules, it will help to simplify our FPGA design.

    Best regards, RY

  • 0 in reply to RY9983
    TI__Mastermind 42545 points

    RY-san,

    Thank you for pointing out that section of the documentation. With that clue I went back to the design documentation and found the confirmation that you are looking for. In the design documentation it states that any 32bit access to the EMIF IP will be broken into accesses to the external bus size with the lowest address presented first regardless of endianess. If you are addressing the FPGA as a 16bit device and you do a 32bit access to the EMIF IP at address 0x30000000, you should get an external access to address 0x0 followed by 0x1 on CE0. This should be true for big endian or little endian settings of the EMIF. Note that the EMIF endian is set by the LENDIAN pin. 

    I am sorry I didn't have that answer for you sooner.

    Regards Bill

  • 0 in reply to Bill Taboada
    Guru 10570 points

    Bill-san,

    Thank you so much for your strong support!
    It was very helpful for us.

    Best regards, RY