Cortex-A15 Cache and MMU setting

Kzk

Hello,

I'd like to measure the access time between Cortex-A15 and DDR3/MSMC-SRAM. CA15 and CA8 are the same as ARMv7. So, I think StarterWare of AM335x can divert K2H. I referred to the exmaple below. The cache setting is almost same. The page table for MMU is changed from AM335x to K2H.

C:\ti\AM335X_StarterWare_02_00_01_01\examples\evmAM335x\cache_mmu

But the access time as enabling cache is slower than another one as disabling cache. I want to understand the difference of setting cache and mmu between CA15 and CA8.

I connected CCS, C66xx_Core0 with xtcievmk2x.gel and CortexA15_1. I ran my program, then I watched ARM Advanced Feature in CCS. MMU Enabled, Data Cache Enabled and Instruction Cache Enabled were checked correctly by my program.

Regards,
Kazu

over 10 years ago

0 Raja over 10 years ago

TI__Guru* 81335 points

Hi Kazu,

I am working with the team to answer your query.

My suggestion would be to go through the ARM documentation to understand difference between CA15 and CA8.

http://www.arm.com/products/processors/cortex-a/

Thanks.

0 Kzk over 10 years ago in reply to Raja

Genius 5785 points

Hi Rajasekaran,

I compared CA8 and CA15 in each documents. I found L2 Cache Auxiliary Control is not present in CA15. This register is set by AM335x StarterWare, but I don't need to set it in CA15. Should I also check somewhere else?

CA8 TRM r3p2 (DDI 0344K/ID060510) : 8.3 Enabling and disabling the L2 cache controller
CA15 TRM r4p0 (DDI 0438I/ID062913) : 7.2.3 Enabling and disabling the L2 cacher

Regards,
Kazu

0 Raja over 10 years ago in reply to Kzk

TI__Guru* 81335 points

Hi Kazu,

We do not any suggestion to check. We currently does not have Starterware on K2X platforms.

Thanks.

0 Kzk over 10 years ago in reply to Raja

Genius 5785 points

Hi Rajasekaran,

I found the example code for enabling I and D cache. I think there is not Auxiliary Control Register in Cortex-A15. Is it necessary to set this register?

K2 ARM CorePac UG (SPRUHJ4)
3.4.3 Enable iCache Example

mrc p15, #0, r1, c1, c0, #1 ; Read Auxiliary Control Register
mov r2, #2
orr r1, r1, r2 ; Set L2EN bit
mcr p15, #0, r1, c1, c0, #1 ; Write Auxiliary Control Register

Regards,
Kazu

0 Raja over 10 years ago in reply to Kzk

TI__Guru* 81335 points

Hi Kazu,

No. It has Auxiliary Control Register. Please refer section 4.3.28 of Resources->ARM Cortex-A15 MPCore Processor Technical Reference Manual.

http://www.arm.com/products/processors/cortex-a/cortex-a15.php

These are non-TI specific questions, I suggest to post the questions to ARM support which you may get more precise answers.

Thanks.

0 Kzk over 10 years ago in reply to Raja

Genius 5785 points

Hi Rajasekaran,

Thank you anyway. I find the difference of ACTLR between CA8 and CA15. I'll ask ARM support about the details.

Regards,
Kazu

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Cortex-A15 Cache and MMU setting