OBSAI AIF2 test between two TMDXEVM6670L

Hello.

I'am trying to connect two TMDXEVM6670L (Rev. A103-1) boards over AIF2 Link 4.

TIMO0 output from DSP on first board is connected to PHYSYNC and RADSYNC inputs of DSP on second board (connected by a wire at 80-pin connectors). I have a chassis (ELMA Blu!one 3000) with crosslinks between AMC slots for ports 17, 18, 19 and 20. AIF Link 4 uses Port 17.

I try to run example aif2WcdmaTestProject from AIF2 LLD (engineering release version 1.1.0.2) with the following configuration:

volatile TestObj testObjTab[TEST_NUM] = {
	{//1st Test - CPRI 4x for DL WCDMA - Link 4
	  "CPRI one link 4x DL", // test name
	  CSL_AIF2_LINK_PROTOCOL_CPRI,
         // link0          link1          link2          link3          link4          link5
	 {0,             0,             0,             0,             1,             0            },  // link enable
	 {4,             4,             4,             4,             4,             4            },  // link rate
	 {DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL },  // outboundDataType
	 {DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16},  // outboundDataWidth
	 {DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL },  // inboundDataType
	 {DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16},  // oinboundDataWidth
	 {CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0}, //Dio engine
	 {1,             0,             0},
	},
	{//2nd Test - OBSAI 4x for DL WCDMA - Link 4
      "OBSAI one link 4x DL", // test name
      CSL_AIF2_LINK_PROTOCOL_OBSAI,
        // link0          link1          link2          link3          link4          link5
         {0,             0,             0,             0,             1,             0            },  // link enable
	 {4,             4,             4,             4,             4,             4            },  // link rate
	 {DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL },  // outboundDataType
	 {DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16},  // outboundDataWidth
	 {DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL,  DATA_TYPE_DL },  // inboundDataType
	 {DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16, DATA_WIDTH_16},  // oinboundDataWidth
     {CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0, CSL_AIF2_DIO_ENGINE_0}, //Dio engine
     {1,             0,             0},
    }}

Macro TEST_NUM is also changed to 2. Also, i have been modify this code (changed CSL_AIF2_LINK_0 to CSL_AIF2_LINK_4):

aif2TraceObj.linkIndex  = CSL_AIF2_LINK_4;//0;

I run builded binary for configuration EVM6670_DSP1 on one board and configuration EVM6670_DSP2 on second board. I have this output on first board (second board output have a same errors):

Beginning AIF2 WCDMA test:
test: CPRI one link 4x DL
AIF CPRI mode
link 0 is disabled
link 1 is disabled
link 2 is disabled
link 3 is disabled
link 4 runs at 4x rate
        outbound data type: DL 
        outbound data width: 16 bit
        inbound data type: DL 
        inbound data width: 16 bit
link 5 is disabled
 Test CPRI one link 4x DL on dsp 1: FAIL

######### AIF2 ERRORS ###########
AT:101 AT PHYT sync input is not aligned to the PHYT counter frame boundary Error.
AT:101 AT RADT sync input is not aligned to the RADT counter frame boundary Error.
RM link4:36068 lcv detection error

######### AIF2 INFO ##############

###############################
test: OBSAI one link 4x DL
AIF OBSAI mode
link 0 is disabled
link 1 is disabled
link 2 is disabled
link 3 is disabled
link 4 runs at 4x rate
        outbound data type: DL 
        outbound data width: 16 bit
        inbound data type: DL 
        inbound data width: 16 bit
link 5 is disabled
 Test OBSAI one link 4x DL on dsp 1: FAIL

######### AIF2 ERRORS ###########
AT:100 AT PHYT sync input is not aligned to the PHYT counter frame boundary Error.
AT:100 AT RADT sync input is not aligned to the RADT counter frame boundary Error.
RM link4:1 los detection error
RM link4:101 lcv detection error
RM link4:2 Indicates that a k28.5 character was not received when it was supposed to have been received.
RM link4:101 OBSAI Only, Indicates that a k30.7 error character was received.

######### AIF2 INFO ##############
RM link4:37 Indicates that the RX state machine changed state

###############################
Some tests have failed

With enabled loopback this test is passed on AIF2 Link 4.

Maybe i'm doing something wrong?

Thanks