Does program always start from core 0 for C6678?

Hi Jie,

When using multicore application, application MUST provide synchronization between cores such that slave cores wait on master core to finish device initialization(SRIO,QMSS,CPPI,..). Core 0 configured as mater core on MCSDK example projects.

Please take a look at below thread:

http://e2e.ti.com/support/embedded/tirtos/f/355/p/340975/1190977.aspx#1190977

Thanks,

Hi Ganapathi,

  Thank you for your helpful information.

  So according to the ReleaseNotes_CPPI_LLD.pdf, theoretically we can configure the initialization from any other cores rather than core 0? Because all the cores are treated equally like in SMP?

  And for single core application, assume no synchronization is needed between cores and each core is running a different application (though I don't know how to do this, I read about MAD, it seems to be a little complex), is each core initialized separately on itself or still initialized by core 0 (master core)?

Thanks,

Jie 

Hi Jie,

During the boot process, the bootloader executes an IDLE command on the secondary CorePacs and keeps the secondary CorePacs waiting for an interrupt. After the application code to be loaded in these secondary CorePacs are loaded and the BOOT_MAGIC_ADDRESS in individual corePacs are populated, the application code in the corePac0 can trigger the IPC interrupt to wake up the secondary cores and branch up to the address specified in the
BOOT_MAGIC_ADDRESS.

Please refer section 2.2 Device Initialization in Bootloader User Guide(SPRUGY5C).

Thanks,

Hi Ganapathi,

   Thank you for your reply. I think I got this same answer for my another thread :http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/345117/1208476.aspx#1208476 where I asked if I could load different applications to different cores at different time. I think that's applicable according to this answer.

  Sorry I may make you confused about my question, but my question here is that, RBL right now configure core 0 to wake up and initialize other cores, but since every core is the same on one chip, can I configure other cores to be like core 0 which wakes up and initialize the remaining cores. I just want to make sure that if all the cores in the multi-core DSP are the same like SMP? (Actually like in normal SMP CPUs, one core or some cores are used to boot up the whole system, but when the system is up, all the cores are equally functioning.)

  Thanks and regards,

Jie

Thank you very much for your help Ganapathi.

Jie