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KeyStone I HyperLink Electrical specifications

Daisuke Maeda
Guru 19845 points

The Hyperlink SerDes has CML IO buffer. For the transmitter, the output voltage swing is set in the range of 760mV to 1220 mV by register. For the receiver, AC-Coupling and the common mode voltage set to 0.7V (VDDT1=1.0V, TERM=001b) are recommended. What are the input threshold voltage levels?

A KeyStone I devices datasheet describes: "All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002."
On the other hand, the SerDes Implementation Guide (SPRABC1) describes: "The HyperLink is a TI-specific peripheral. There is no industry standard for it."

Does the HyperLink SerDes comply with the XAUI Electrical Specification, IEEE 802.3ae-2002?

Best regards,

Daisuke

 

  • 0
    Guru 19845 points

    Hi,

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Guru 19845 points

    Hi,

    Is the answer to my question described in a document of KeyStone I?

    Section 7.4.3 in SPRABI2C describes: "The SerDes interfaces use CML logic. Compatibility to LVDS signals is possible and is described in Section 7." I cannot find the description in section 7. Where is there it?

    What is the range of input voltage? Is the minimum amplitude 200mVp-p? Is the range of maximum input voltage 0V to 1.0V (CVDD1=1.0V)?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Guru* 81335 points

    Hi Daisuke,

    We working with expert to answer this post. Thank you for your patience.

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    The HyperLink interface is a TI specific SerDes implementation designed for very short processor-to-processor connections. The electrical characteristics of the signal are defined by the XAUI Electrical Specification, IEEE 802.3ae-2002. The protocol associated with the data transfer is not part of that standard. Currently, HyperLink is only supported by TI processors. If you follow the implementation guideline concerning the length of the routing, the impedance and the adjacent reference plane, the interface should operate correctly.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19845 points

    Hi Bill and Rajasekaran K,

    Thank you for your reply.

    In XAUI Electrical characteristics in IEEE 802.3ae-2002, for the input signal amplitude, it is described: "Since the XAUI receiver is AC coupled to the XAUI, the absolute voltage levels with respect to the receiver ground are dependent on the receiver implementation."

    For the receiver, is the range of maximum input voltage 0V to 1.3V (CVDD1=VDDT1=1.0V)?

    For the transmitter, the recommended output voltage swing is 1005mVdfpp (SWING=0111b). For the receiver, the recommended common mode voltage is 0.7V (VDDT1=1.0V, TERM=001b). If no attenuation to the receiver, input voltage to the receiver is 0.1975V (0.7V-0.5025V) to 1.2025V (0.7V+0.5025V).

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    The input range will not be exceeded by another HyperLink driver. Are you trying to connect something other than a TI HyperLink driver to your HyperLink receiver?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19845 points

    Hi Bill,
     
    Thank you for your reply.

    Our customer connects C66 HyperLink to FPGA HyperLink.

    I understand that the 1220mV output voltage swing can be used if the AC-Coupling and the 0.7V common mode voltage and the equalization are used at receiver side.

    Is my understanding correct?

    Best regards,
     
    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    The note from the internal specification states that when the 0.7V common mode voltage is used then the input signal amplitude must not exceed 1200mV differential peak-to-peak.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 19845 points

    Hi Bill,
     
    Thank you for your reply.
     
    I understand that the input signal voltage must not exceed the input voltage range in Absolute Maximum Ratings.
     
    Best regards,
     
    Daisuke