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6678 Clock H/W Design

Hi, all

I am using the 6678 EVM board and design a new board.

Is there a problem I want to design a clock frequency synchronization, as shown below?

Thanks,

Regards,

  • Hello Gyosun,

    I believe there is no problem in implementing the above circuitry for clock synchronization as long as you meet the clocking requirements in hardware design guide. Is there any specific requirement to go for clock synchronization ? Since It is not necessary that the clocks of the DSP be synchronous.

    You may also consider some recommended clocking solutions in section 3.6 Clocking and Clock Trees in hardware design guide.

    Regards,
    Senthil