Hi,
Before i speak on to the question, here is the detail of what we are trying :
For PDCCH channel, design :
1. CRC, Convolution Encoding and Rate Matching using BCP for each DCI (multiple BCP invocations, once per DCI)
2. Concatenation of Rate-Matched output of each DCI in SW
3. Scrambling and Modulation of this concatenated output using MOD module of BCP.
Here are the changes done in the example project :
info.inputDataLen = maxPossiblePdcchBits; ( 344 bits ( Nreg * 8 ) )
info.totalSymbolCount = maxPossiblePdcchBits/2;
info.subFrameNum=pdcchInfo->subframeNum; // value is 0
info.cellID = pdcchInfo->phyCellId; // value is 10
info.tbSize= maxPossiblePdcchBits * 8 // value is 344 * 8
cinit value : ((uint32_t)(info->subFrameNum* (1 << 9)) + info->cellID); // value is 10
In a scratch buffer, i am unpacking 18 bytes of data(144 bits) (other 200 bytes being zero(NIL)) which is equal to aggregation level * 2 (the amount of bits to we worked upon by MOD module(input))
I am using compressed mode
Sample :
For software :
For input : 10101100 0111111 01010010
scrambled output : 11001110 01010000 00100110
modulated ouput : 1101001010111111(I & Q same), 0010110101000001(I&Q same), 1101001010111111(I&Q same)
On BCP :
For the same input
modulated output : 1111110100101100(I & Q same), 0000001011010100(I&Q same), 1111110100101100(I&Q same)
could you please tell, what is wrong in this design(save for performance issues) and the reason for output mismatch?
EVM. DSP C6670.
MCSDK version : mcsdk_2_01_02_06
Best Regards
Ujjwal
