Hello,
I am using the TAS2505 audio CODEC for my application in the following configuration:
- Master mode (receiving external clock, generating bit and word clocks)
- No FIR
- 16 bits sample/44.1KHz/big endian
- Loud speaker output class D amplifier
What I experience is that the audio seems to clip at some moments. (I will try to read out the clipping bit today to have prove) I have tried the different amplifier settings of the device, but no improvement was found. On the logic analyser the I2S stream seems to contain the correct samples.
I have reduced the sample loudness to half the volume. This comes at the end as 8 bits of the sample used. This plays fine (no cuts in the audio), although there is a loud noise present in the audio but the sound is recognizable. The noise is probably caused by the extra analog amplification required to compensate the volume reduction in the samples (also quantization noise), or because of a wrong configuration for the use of the most significant Byte.
My question is what is wrong in my configuration that I cannot use the full 16 bits configuration, and how can I get rid of the noise? I did not initialize the FIR filter(s), can you confirm the FIR is not required?
Please find the register settings below.
Thanks for your help,
John
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These are my registers:
/* TAS2505 Register Addresses */
#define ASM_PAGE_SELECT_REG 0x00 /* TAS2505 Page Select Register Address */
#define ASM_PAGE0_REG3 0x03 /* TAS2505 Page0 Register 3 Address */
#define ASM_PAGE0_DAC_CH_SETUP_REG2 0x40 /* TAS2505 Page 0 DAC Channel Setup Register Address */
#define ASM_PAGE1_SPEAKER_VOL_CTRL 0x2E /* TAS2505 Page 0 DAC Channel Setup Register Address */ /* TAS2505 Register Settings */
#define ASM_PAGE0_SELECT_REG_REG0 0x00 /* Select Page 0 */
#define ASM_PAGE1_SELECT_REG_REG0 0x01 /* Select Page 1 */ #define ASM_SOFTWARE_RESET_REG1 0x01 /* Software Reset */
/* Page 0 Settings */ #define ASM_RESERVED_REG3 0x00 /* Reset Value of Register 3 Page 0 */
#define ASM_CLK_SETTINGS_REG1_REG4 0x00 /* MLCK pin is input to PLL, MCLK pin is CODEC_CLKIN */ #define ASM_CLK_SETTINGS_REG2_REG5 0x11 /* PLL shut off */
#define ASM_CLK_SETTINGS_REG3_REG6 0x04 /* Default Value - PLL J Value */ #define ASM_CLK_SETTINGS_REG4_REG7 0x00 /* Default Value - PLL D Value MSB */
#define ASM_CLK_SETTINGS_REG5_REG8 0x00 /* Default Value - PLL D Value LSB */ #define ASM_RESERVED_REG9_TO_REG10 0x00 /* Default Value */
#define ASM_CLK_SER_NDAC_SETTING_REG11 0x85 /* NDAC = 5 */
#define ASM_CLK_SER_MDAC_SETTING_REG12 0x83 /* MDAC = 3 */
#define ASM_CLK_SER_DOSR_MSB_SETTING_REG13 0x00 /* DOSR = 96 */
#define ASM_CLK_SER_DOSR_LSB_SETTING_REG14 0x40 /* DOSR = 96 */
#define ASM_RESERVED_REG15 0x02 /* Default Value */
#define ASM_RESERVED_REG16_TO_REG24 0x00 /* Default Value */
#define ASM_CLK_SETTINGS_REG10_REG25 0x00 /* Multiplexers: CDIV_CLKIN = MCLK */
#define ASM_CLK_SETTINGS_REG11_REG26 0x01 /* CLK M Divider */
#define ASM_AUDIO_INTERFACE_SETTING_REG1_REG27 0x0C /* I2S Data Interface, 16bit Word length, BCLK is Output, WCLK is Output */
#define ASM_AUDIO_INTERFACE_SETTING_REG2_REG28 0x00 /* BCLK Data Offset = 0 */
#define ASM_AUDIO_INTERFACE_SETTING_REG3_REG29 0x01 /* Default Bit Clock polarity, BCLK and WCLK Buffers are powered up and BDIV_CLKIN = DAC_MOD_CLK */
#define ASM_CLK_SETTINGS_REG12_REG30 0x82 /* BCLK N Divider = 2 */
#define ASM_AUDIO_INTERFACE_SETTING_REG4_REG31 0x00 #define ASM_AUDIO_INTERFACE_SETTING_REG5_REG32 0x00
#define ASM_AUDIO_INTERFACE_SETTING_REG6_REG33 0x00 #define ASM_DIG_INTERFACE_MISC_REG34 0x00
#define ASM_RESERVED_REG35_TO_REG36 0x00 /* Default Value */ #define ASM_DAC_FLAG_REG1_REG37 0x00 /* Default Value */
#define ASM_DAC_FLAG_REG2_REG38 0x00 /* Default Value */ #define ASM_RESERVED_REG39_TO_REG41 0x00 /* Default Value */
#define ASM_STICKY_FLAG_REG1_REG42 0x00 /* Default Value */ #define ASM_INT_FLAG_REG1_REG43 0x00
#define ASM_STICKY_FLAG_REG2_REG44 0x00 /* Default Value */ #define ASM_RESERVED_REG45 0x00 /* Default Value */
#define ASM_INT_FLAG_REG2_REG46 0x00 #define ASM_RESERVED_REG47 0x00 /* Default Value */
#define ASM_INT1_CTRL_REG_REG48 0x00 /* Default Value */ #define ASM_INT2_CTRL_REG_REG49 0x00 /* Default Value */
#define ASM_RESERVED_REG50_TO_REG51 0x00 /* Default Value */ #define ASM_GPIODOUT_CTRL_REG_REG52 0x00
#define ASM_DOUT_CTRL_REG_REG53 0x00 /* DOUT Buskeeper disabled */
#define ASM_DIN_CTRL_REG_REG54 0x02 /* DIN is enabled */
#define ASM_MISO_CTRL_REG_REG55 0x00 /* MISO Buffer Disabled */
#define ASM_SCLK_CTRL_REG_REG56 0x00 /* SCLK is Disabled */
#define ASM_RESERVED_REG57_TO_REG59 0x00 /* reserved value */
#define ASM_PAGE0_DAC_INSTR_SET_REG60 0x02 /* DAC Signal Processing Block PRB_P2: OK */
#define ASM_RESERVED_REG61_TO_REG62 0x00 /* reserved value */
#define ASM_DAC_CHANNEL_SETUP_REG1_REG63 0xA6 /* DAC Channel Powered Up, DAC data is picked from left and right channel */
#define ASM_DAC_CHANNEL_SETUP_REG2_REG64 0x04 /* not auto muted and not muted at all */
#define ASM_DAC_CHANNEL_DIG_DAC_VOLUME_REG65 0xF8 //0x01 /* Digital Volume Setting */
#define ASM_RESERVED_REG66_TO_REG74 0x00 /* reserved value */
#define ASM_RESERVED_REG75 0xEE /* reserved value */
#define ASM_RESERVED_REG76 0x10 /* reserved value */
#define ASM_RESERVED_REG77 0xD8 /* reserved value */ #define ASM_RESERVED_REG78 0x7E /* reserved value */ #define ASM_RESERVED_REG79 0xE3 /* reserved value */
#define ASM_RESERVED_REG80_TO_REG127 0x00 /* reserved value */
/* Page 1 Settings */ #define ASM_RESERVED 0x00 /* reserved value */
#define ASM_REFPOR_CTRL_REG_REG1 0x10 /* Master Reference powered up */
#define ASM_LDO_CTRL_REG_REG2 0x0C /* PLL and HP Level Shifter powered up */
#define ASM_PLAYBACK_CONFIG_REG_REG3 0x24 /* DAC in Mode PTM_P1, DAC is enabled with high performance mode */
#define ASM_DACPGA_CTRL_REG_REG8 0x80 /* Soft Stepping of DAC disabled */
#define ASM_OUTPIT_DRIVER_CTRL_REG_REG9 0x00 /* AINL, AINR & HPL output powered Down */
#define ASM_COMMON_MODE_CTRL_REG_REG10 0x04 /* Full Chip Common Mode is 0.9V, Headphone output full drive ability */ //@@@ 0x00
#define ASM_HP_OVERCURRENT_CONFIG_REG_REG11 0x10 /* No Debounce is used for Over Current detection */
#define ASM_HP_ROUTING_SELECTION_REG_REG12 0x00 /* DAC putput is not routed directly to HP Driver */
#define ASM_HP_DRIVER_GAIN_SETTING_REG_REG16 0x40 /* HP Driver is muted */
#define ASM_AINL_VOL_CTRL_SETTING_REG24 0x00 /* Mixer P and M not forced enabled, AINL Volume 0db */ ///@@@ 0x80 #define ASM_AINR_VOL_CTRL_SETTING_REG25 0x00 /* Mixer P and M not forced enabled, AINR Volume 0db */
#define ASM_SPEAKER_AMP_CTRL_REG_REG45 0x02 /* Speaker output driver is powered up*/
#define ASM_SPEAKER_VOL_CTRL_REG_REG46 0x00 /* Speaker Volume gain: 0x00 = 0db, 0x30 = -24db, 0x48 = -36db */
#define ASM_SPEAKER_AMP_VOL_CTRL_REG2_REG48 0x20 /* Speaker Driver Volume = 6dB */
