Change frequency on c6678

Hi,

1.- In my application, is interesting that when the cores have low workload, down the frequency (for example of 1.24GHz to 800MHz), can do, without reset the cores?

Yes.

2.- For change the frequency is ALWAYS necessary access to GEL

No. User can also initialize/modify the CPU frequency in our test application itself.

Thanks,

Hi,

Take a look at platform.c file for core PLL initialization: \ti\pdk_C6678_1_1_2_6\packages\ti\platform\evmc6678l\platform_lib\src\

        /* PLLC module handle structure */
        if (p_flags->pll) {

            /* Set the Core PLL */
            /* Clear local data structures */
            memset(&pllc_hwSetup, 0, sizeof(PllcHwSetup));

            /* Setup PLLC hardware parameters */
            pllc_hwSetup.divEnable  = (CSL_BitMask32) (PLLC_DIVEN_PLLDIV2 |
                                                       PLLC_DIVEN_PLLDIV5 |
                                                       PLLC_DIVEN_PLLDIV8) ;

            /* Setup PLLC hardware parameters */        
            pllc_hwSetup.pllM       = 
                    (((p_config->pllm) ? p_config->pllm : PLATFORM_PLL1_PLLM_val) - 1);
            pllc_hwSetup.preDiv   = PLATFORM_PLL_PREDIV_val - 1;
            pllc_hwSetup.pllDiv2  = PLATFORM_PLLDIV2_val - 1;
            pllc_hwSetup.pllDiv5  = PLATFORM_PLLDIV5_val - 1;
            pllc_hwSetup.pllDiv8  = PLATFORM_PLLDIV8_val - 1;
            pllc_hwSetup.postDiv  = PLATFORM_PLL_POSTDIV_val -1;

            /* set Pll */
            status = CorePllcHwSetup (&pllc_hwSetup);

            if (status != CSL_SOK) {
                 platform_errno = PLATFORM_ERRNO_PLL_SETUP;
                return ( (Platform_STATUS) Platform_EFAIL);
            }

            /* Read back */
            status = CorePllcGetHwSetup (&pllc_hwSetupRead);

            if (status != CSL_SOK) {
                platform_errno = PLATFORM_ERRNO_PLL_SETUP;
                return ( (Platform_STATUS) Platform_EFAIL);
            }

Thanks,

Luis,

There is no register to read the PLL output stability. However some alternate ways are there to set the PLL clock stable and check if the PLL initialization done without any errors.

1. If executing the PLL initialization sequence immediately after device power-up, you must allow time for the PLL to become stable. PLL stabilization time is 100 µs.

2. Below are the reserved pins on the device which will indicate the status of the main PLL lock, DDR3 PLL lock and PA PLL lock. These pins can be checked to identify whether or not the device encountered the error condition.
• RSV20 - COREPLLLOCK
• RSV21 - DDR3PLLLOCK
• RSV22 - PAPLLLOCK

Regards,
Senthil