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Partial Automatic Leveling vs Full Automatic leveling

giorgos tsoumplekas
Expert 1840 points

Dear all,

We are working on C6657 and we try to configure the DDR3 following up the examples that provided by TI but in respect to the design requirements of our chip.

We have noticed  that some times the DDR3 is unstable. In errata documet we went throught the DDR3 Automatic Leveling Issue advisor 3 and we want to apply the workaround 3 (Full Automatic leveling). Do you believe that this will solve the problem?

In section  3.3 I cannot understand what means "There must be no writes to any fixed ratio registers when full automatic leveling is used."

What are the differences in the configuration between the two ways of leveling?

The registers SDRAM_TIM_1, SDRAM_TIM_2, SDRAM_TIM_3 should be confugired  in both of them?

Moreover , should be  the registers 2 - 24  configured  as well?

Best regards

George 

  • 0
    TI__Mastermind 46460 points

    George,

    Please search the E2E database for the phrase "partial automatic leveling".  This has been answered several times.  We recommend that you use the Partial Automatic Leveling as implemented in the latest C6657 GEL file and in the MCSDK code.  You will need to properly use the PHY_CALC and REG_CALC spreadsheet tools that accompany the KeyStone I DDR3 Initialization Application Report SPRABL2D.  If you are having leveling problems, you probably have layout deficiencies.  There are also many threads on that topic.  Please refer to the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B) and the Hardware Design Guide for KeyStone I Devices Application Report (SPRABI2C).

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1840 points

    Hello,

    I understand that is annoying to ask things that are repeated.  But  some questions cannot completely cover other issues. In any case , why is recomended to use partial automatic leveling instead of full automatic?

    Automatic leveling is provided as workaround in sprz381b document ,advisor 3.

    Best regards

    George

  • 0 in reply to giorgos tsoumplekas
    TI__Mastermind 46460 points

    George,

    This post answers the question:

    C6674 DDR3: Leave incremental leveling enabled indefinitely?:

    These are other similar posts containing additional information:

    Keystone I DDR3 Leveling Issue:

    DDR3 Readback issue and DDR3 leveling questions:

    C6657 DDR3 DQ vs DQS timing:

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    George,

    You next question is going to be about proper board and software commissioning.  Please see this link:

    DDR3 settings on C6678:

    Here is a more complete summary lifted from an INT-E2E post:

    The design team needs to show that they have completed their design validation steps.  Please create a report showing that the length matching rules have been met.  This can be generated by many PCB layout tools.  Alternately, it can be generated by hand.

    The DQS and CLK routed lengths are then copied into the PHY_CALC worksheet.  The latest changes reflected in PHY_CALC version 11 were created specifically to highlight that the registers were different for C665x.  PHY_CALC is a worksheet that can be downloaded from a link in the KS1 DDR3 Initialization App Note (SPRABL2B).  V11 is the latest version.

    The most recent versions of the DDR3 User Guide and the DDR3 Initialization App Note correctly indicate the PHY registers for C665x devices.  These are available on the TI web pages.

    KS1 DDR3 User Guide (SPRUGV8D):

    KS1 DDR3 Initialization App Note (SPRABL2B):

    REG_CALC is a worksheet that can be downloaded from a link in the KS1 DDR3 Initialization App Note (SPRABL2B) along with the PHY_CALC worksheet but it is also copied here (V4 is the latest version):

    The results from the PHY_CALC and REG_CALC worksheets are then used to configure the DDR3 initialization code.  We recommend that you validate operation
    with a CCS GEL file since this is most simple and is a very robust means to validate operation.  The C6657 GEL available with CCS shows the correct register use.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    George,

    The E2E response mailed out is missing the links.  Please view the responses in your browser.

    Tom