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How to start with JESD204A in k2l 6630

striker qian
Intellectual 755 points

Hi , expert

We have a custom k2l board and now we want to use the jesd204 to receive some raw data from FPGA (We already have 4 lanes connections).

My question : Is there any out-of-box demo to demonstrate that ?  I'm not sure whether iqnet demos in pdk will help.

Since I am not so aware of jesd  and our purpose is  just to use it like SRIO in DirectIO mode, we want it as simple as possible.

Thanks,

striker

 

 

  • 0
    TI__Mastermind 37500 points

    Hello,

    There are two general operating modes for DFE-JESD204

       (a) using the DFE to transport synchronized data sets through JESD204B.  The DFE performs signal processing functions. 

       (b) (new) not yet released is a signal processing bypass function, where the DFE signal processing functions are not used.  JESD is transported either through DFE with little or no signal processing, or in special cases can bypass DFE completely.

    The current adjacent market design #1, uses (a) to transport 1 complex IQ stream over 2 JESD lanes, at a line rate of 4.9152Gbps(2x60 demo).  Serdes 2-0 lane 0 (I), Serdes 2-0 lane 1 (Q).  The Design Guide, and Getting Started guide for this design are on the TI My Secure Software site.  You need to contact your marketing engineer, or Field Application Engineer from TI to get access to this software. 

    The IQ Data set for 2x60 example is a zero IF transmit and receive set, sampled at 245.76Msps.  There are 2 carriers in the antenna stream, each IF mixed to +/- 35 Mhz.   There is a revised design 2x75, 368.64Msps, line rate 7.3728G (this is just a higher bandwidth with two 75Mhz BW carriers spaced -43.5, 43.5Mhz).

    The software has DDR memory transport to IQN to DFE through channel processing to Tx stream processing to JESD Tx.  Then JESD Rx to Rx/Fdbk stream processing to channel processing to IQN and back to memory.   There is a "playback" program that creates the PktDMA usage, programs the IQN configuration, programs the DFE configuration, programs the Serdes configuration, and monitors specific variables in the DSP to save or load data sets to a file.

    In your FPGA you can initially loopback JESD Tx0 -> JESD Rx0, JESD Tx1 -> JESD Rx1, and loopback JESD Sync Out0 to JESD Sync In0.   Using the your FPGA and this configuration, or using the DFE-JESD Lane loopback, you should see the two channels mixed, and combined into a stream, or mixed from a stream for the 2 Rx channels.

    There DFE has baseband loopback DFE configurations, that allow testing the of the internal Lamarr signal processing, JESD lane loopback to include the DFE processing, coupled with the FPGA in loopback is the next step.

    Future design #3 will illustrate the bypass DFE type functions. 

    Regards,

    Joe Quintal

  • 0 in reply to Radio-Joe
    Intellectual 350 points
    So how do I get the design and getting started guide for this as well as the reference design itself?