Power domain disable does not affect PDSTAT register

Rao Munzir

Other Parts Discussed in Thread: 66AK2H14

Hi,

I am using EVMK2H and trying to disable power of DDR3 that is PD 16. I am following SPRUGV4C as reference and did try to disable power using following code snippet. but my PDSTAT reigster that is at 0x02350240 shows 0x301 that power is enabled. What am I doing wrong?

mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * 24 )); 
mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * 24 )); 
pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * 16 )); 
GEL_TextOut("Power disable start of DDR3 .\n"); 
while (PSC_PTSTAT & (0x1 << 16) != 0 ); 
*pdctl = (*pdctl) & 0xfffffffe; 
PSC_PTCMD = (PSC_PTCMD) | (0x1<<16); 
while (PSC_PTSTAT & (0x1 << 16) != 0 ); 
GEL_TextOut("Power disable end of DDR3.\n");

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi Rao,

Please check below post from Aditya helps you to disable power domain,

e2e.ti.com/.../387871

Thank you.

0 Rao Munzir over 9 years ago in reply to Raja

Expert 1070 points

   	 GEL_TextOut("Domain disable start of DDR3B.\n");
   	 while (PSC_PTSTAT & (0x1 >> 16) == 1 );
   	 *pdctl &= 0xfffff0fff;
   	 *pdctl &= 0xFFFFFFFE;
         *pdctl = 0;
          PSC_PTCMD = 0x1 << 16;
          while (PSC_PTSTAT & (0x1 >> 16) == 1 );
	   	 GEL_TextOut("Domain disable end of DDR3B .\n");

thanks,

I did as that post you indicated but DDR3 power domain is still showing the status of 0x301.

Above is code:

0 Rao Munzir over 9 years ago in reply to Rao Munzir

Expert 1070 points

Hi,

It seems that DDR3A and DDR3B power down modes are not working for 66AK2H14 in EVM boards. We have implemented the procedure specified in the 66AK2h14 datasheets. We have also tried the procedure mentioned in your TI community thread.

We can power down other modules such as MSMC RAM and PCIe using the specified procedure.

Please let us know whether power down mode working in 66AK2H14 for DDR's and if its working then what is the correct procedure to bring power down for DDR's.

0 Rao Munzir over 9 years ago in reply to Rao Munzir

Expert 1070 points

any update guys?

0 Senthilkumar Srinivasan over 9 years ago in reply to Rao Munzir

TI__Mastermind 43660 points

Rao,

Posting the suggestions/questions from the other thread that you have created. Could you please try this and let us know.

Which memory are you using to run the "disable the DDR3" code ?
Can you use MSMC RAM or internal RAM L2 etc., ?
BTW, You can also save the power by enabling the power down mode in STATUS register of DDR3.

Regards,
Senthil

0 Titusrathinaraj Stalin over 9 years ago in reply to Senthilkumar Srinivasan

TI__Guru** 116100 points

Dear Rao,
I haven't seen this post.
It looks like you are trying to disable the DDR3 in gel file right ?
Can you provide that code snippet ?

0 Rao Munzir over 9 years ago in reply to Senthilkumar Srinivasan

Expert 1070 points

Yes I am using internal ram and trying to achieve it gel file. But I want to completely shut down DDR3 for some testing purpose. PWRDWN bit in DDR3 status register in Read only as per SPRUHN7C page 51. here is the code snippet:

mdctl = ( unsigned int* )(PSC_MDCTL_BASE + ( 4 * 24 ));
mdstat = ( unsigned int* )( PSC_MDSTAT_BASE + ( 4 * 24 ));
pdctl = ( unsigned int* )(PSC_PDCTL_BASE + ( 4 * 16 ));

GEL_TextOut("Module disable start of DDR3 t.\n");
while (PSC_PTSTAT & (0x1 >> 16) == 1 );
*pdctl &= 0xfffff0fff;
*pdctl &= 0xFFFFFFFE;
*pdctl = 0;
PSC_PTCMD = 0x1 << 16;
while (PSC_PTSTAT & (0x1 >> 16) == 1 );

GEL_TextOut("Module disable end of DDR3.\n");

0 Titusrathinaraj Stalin over 9 years ago in reply to Rao Munzir

TI__Guru** 116100 points

Thanks Rao, let me try and update you.

Processors

Processors forum

Power domain disable does not affect PDSTAT register