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66AK2L06 JESD configuration and limitations

Edmund Pirali99
Intellectual 300 points

Other Parts Discussed in Thread: 66AK2L06

We are looking to replace and FPGA in our design with the Keystone 66AK2L06 chip. The main application is to use the JESD interface (4 lanes) with an analog devices A/D. Problem is the documentation for this chip is some of the least complete and obtuse I have seen from TI. The Keystone II SerDes guide states that only TI generated and supported PHY configurations are available and provides a very small table of values that can be used. If this is the case it would rule out using a vast majority of ADC with JSED sample rates that are not in the very limited table (see below).


Is this really the case? Is this part only have a very limited use for JESD data acquisition? That would defeat the purpose of the part. Where can I get some definitive information about available and possible configurations quickly?

Thanks.

-----

Config Baud Rate

1X Rate (Gbps)

1/2X Rate (Gbps)

1/4X Rate (Gbps)

Ref Clock (MHz)

Bit Width

6.144 Gbps

6.144

3.072

- (1)

122.88

20

6.144 Gbps

6.144

3.072

-

153.6

20

7.3728 Gbps

7.3728

3.6864

-

122.88

20

9.8304 Gbps

-

4.9152

2.4576

122.88

20
  • 0
    TI__Guru* 81335 points

    Hi Edmund,

    Please refer below thread for some help.

    Thank you.

  • 0 in reply to Raja
    Intellectual 300 points

    Thanks for the link, but it's not very helpful. First it discusses how it MAY be possible in the future to  bypass processing in the DFE. I am not interested in any processing in the DFE front end, only acquiring data via JESD.

    My primary question about configuration of SERDES AND possible JESD data rates. The Post says nothing about this. I need information about what data rates AND TRANSFER MODES are possible and how to configure the SERDES and the DFE.

    Without this information I am forced to revert to an FPGA based design.

    Thanks.

  • 0 in reply to Raja
    Intellectual 300 points

    Ok I will try once more before moving on. I need to know whether the JESD can be configured (even with TIs help) to support other rates WE MUST HAVE before we commit to this part, and whether we can bypass the front end processing and only capture JESD data DIRECTLY to DDR memory (at a rate of of close to 2 GB/sec).

    If we can't find out some information soon I am forced to move on.

    Can you please respond? I understand first posts get immediate but not necessarily useful replies, but then threads like this are left to die. Can you route me to somewhere in TI that can provide fast answers?

    Thanks.

  • 0 in reply to Edmund Pirali99
    TI__Mastermind 37500 points

    Hello Edmund,

    There is no direct support with 66AK2L06 with JESD for data converters higher than the max sample rate input below.  Also the DFE decimates or interpolates to the maximum Baseband rate. 

    You would need to use CPRI, FPGA, JESD to transcode 16LTE20 Antenna containers, for each 983.04Msps real ADC.   The H12, H14 processors have 6 AIF2 lanes, the 66AK2L06 (PG2) will have 2 AIL lanes each with CPRI 16x.

    JESD / DFE limits

    The JESD transfers data into the DFE.  There is a bypass capability, but the bypass is still limited to the maximum IQ rate of an IQN channel.

    PG1 device - 1 antenna container (channel) 122.88Msps complex, 245.76Msps real

    PG2 device - 1 antenna container (channel) 184.32Msps complex, 368.64Msps real

    These limits are based on the DFE clock, JESD parameter limits, and DFE limits.

       a) DFE clock is limited to 245.76 or 368.64Mhz for standard configurations

       b) JESD limitations are both line rate, and JESD format limited

               there are 1, 2, 4 lanes

               the standard Serdes line rate is 2.4576G, 3.6864G, 4.9152G, 7.3728G

               the standard JESD parameters are supported, F=2,3,8; K = 4..32

       c) DFE limits have both the input side, and output to IQN side

               input side limits are based on the number of lanes and F parameter and DFE clock

                   DFE input rate is based on gating the DFE clock of 245.76 or 368.64, typical data converter rates are

                   61.44, 92.16, 122.88, 184.32, 245.76, 368.64, 491.52(R), 737.28(R)

                    max rate for radio input or output is based on the DFE input rate above

                        for a single Tx out, Rx in you can have a 368.64Msps complex, for Rx in can be 737.28Msps real (1st Nyq zone)

                        you can have (2) Tx out, one Rx, and one Fdbk at the above rate.

                output side limits

                    PG1 device - 1 antenna container (channel) 122.88Msps complex, 245.76Msps real

                                          n (where n > 1)  antenna container (channels) = DFEclk/(2*numberchannels) 

                    PG2 device - n antenna container (channels) = DFEclk/(2*numberchannels)

    Regards,

    Joe Quintal