Cannot clear EDMA3 synchronization event input from a GPIO pin

Ari Poutanen

Hi,

I have yet another problem in using the EDMA3 in the C6638 K2H EVM board rev 4.0.

I use the GPIO8 as the synchronization event for the DMA transfers but every time I enable the channel either by writing into the EESR register or by calling the "EDMA3_DRV_enableTransfer()", the transfer immediately begins regardless of the electrical state of the GPIO8 pin.

I guess there is a C66 CorePac event (or interrupt) register which I should clear before enabling the event, but so far have not found such a register with the emulator or from numerous forums and specifications.

I have checked the EVM board schematics to see if there is some circuit driving the GPIO8 pin but I could not find anything different to the other pins (like GPIO10) which I use as an interrupt source for another purpose at the same time without any problems. Also, I cannot see anything happening in the pin with an oscilloscope or in the GPIO "data in" register.

When triggering the GPIO8 EDMA input event manually in the software by writing into the ESR register, it works perfectly without any problems, but not with an external source like already mentioned above.

I have not specified any event combiner or interrupt service routine for the GPIO8 because I want to use it only as a EDMA input without interrupting the CPU with it. So I think I should do some event clearing like in an interrupt handler, but just don't know in details how.

Best regards,

Ari

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

I think, it is a hardware event tied to a particular DMA channel and we need to check with schematics to validate this.

We will work on this and will let you know the update shortly.

Thanks & regards,
Sivaraj K

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Hello Ari,

As you mentioned, there is no issue with the GPIO8 circuitry and also it is similar to the GPIO10. We will try to reproduce this in our EVM and update you.

Regards,
Senthil

0 Sivaraj Kuppuraj over 9 years ago in reply to Senthilkumar Srinivasan

TI__Mastermind 35645 points

Hi,

In my understanding, if the DSP services system events which are specified directly in the interrupt selector, then there is no need to read or clear the EVTFLAGx registers in the Interrupt Controller but you must use event flags within an interrupt service routine or an exception service routine when servicing combined system events. Usually, the DSP’s interrupt flag register or exception flag register would tell the DSP that a combined event has occurred, then the service routine must use the event flag register to determine the exact cause.

It is also important to note that within the service routine, the appropriate event flag register bits must be cleared by software in order to receive a subsequent event. If the event flag does not clear, then a new system event will not be recognized.

Please check Table 9-3 for the available C66x CorePac interrupt controller registers from the CorePac user guide below and other than these, you wouldn't find any event/interrupt register to clear before enabling any event:

http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

-------------------------------------------------------------------------------------------------------

0 Ari Poutanen over 9 years ago in reply to Sivaraj Kuppuraj

Expert 1140 points

Hi,

thanks for your replies.

I have studied the event flags. The GPIO8 event activates immediately when I enable the GPIO bank 0 interrupt. See my INTC registers below. This happens although I have powered off my peripherals so that it is 100% sure they don't drive the pin. Furthermore, after disabling the GPIO bank 0 interrupt, clearing the EVTFLAG for the event 82 and re-enabling the GPIO bank 0 interrupt, the EVTFLAG for 82 jumps back up. By running the debugger and monitoring the EDMA PaRAM field "CCNT" I have seen the event 82 activates about 10 times per second because the "CCNT" drops from the value 16 into about 5 in about one second. I just cannot see anything in the oscilloscope or in the GPIO INDATA register. This is very strange.

Before enabling the GPIO bank 0 interrupts and the EDMA channel:

0x01800000: 00000000    EVTFLAG 0
0x01800004:00000000    EVTFLAG 1
0x01800008:00100001    EVTFLAG 2
0x0180000C:00000000    EVTFLAG 3

0x01800080:7BFFFFFF    EVT MASK 0
0x01800084:FFFFFFFF    EVT MASK 1
0x01800088:FFFFFFFF    EVT MASK 2
0x0180008C:FFFFFFFF   EVT MASK 3

0x018000A0:00000000    masked EVTFLAG 0
0x018000A4:00000000    masked EVTFLAG 1
0x018000A8:00000000   masked EVTFLAG 2
0x018000AC:00000000   masked EVTFLAG 3

After enabling the GPIO bank 0 interrupts only, not the EDMA channel, by writing "1" directly into the GPIO register "binten" with the emulator.

0x01800000: 00000000    EVTFLAG 0
0x01800004:00000000    EVTFLAG 1
0x01800008:00140001    EVTFLAG 2    <-- 4 = GPIO8 (= event 82)
0x0180000C:00000000    EVTFLAG 3

0x01800080:7BFFFFFF    EVT MASK 0
0x01800084:FFFFFFFF    EVT MASK 1
0x01800088:FFFFFFFF    EVT MASK 2
0x0180008C:FFFFFFFF   EVT MASK 3

0x018000A0:00000000    masked EVTFLAG 0
0x018000A4:00000000    masked EVTFLAG 1
0x018000A8:00000000   masked EVTFLAG 2
0x018000AC:00000000   masked EVTFLAG 3

From the registers above can be seen that the raw status of the event 82 (GPIO8) becomes active but the masked status keeps "0". The event 82 is masked so that it will not produce interrupts. Obviously it still can act as an EDMA input event, but what makes it to activate?

Did you try the GPIO8 EDMA event in your EVM board?

BRS, Ari

0 Ari Poutanen over 9 years ago in reply to Ari Poutanen

Expert 1140 points

Hi,

a small update from this morning:

I disconnected all the cables from all the peripherals so that the EVM kit is a stand-alone system.

Then I powerd the EVM up and immediately connected the emulator on DSP0. Now, if I understand right, all the CPU cores are halted so that they cannot affect to the events.

Then, using the emulator, I configured all the GPIO pins 0...15 to inputs and enabled rising edge interrupts for all of them.

Finally I enabled the GPIO bank 0 interrupt.

Result: All the other events stay 0, but the event 82 rises up immediately when the bank interrupts are enabled.

Can my EVM board be broken?

Regards,

Ari

0 Ari Poutanen over 9 years ago in reply to Ari Poutanen

Expert 1140 points

Hi,

I disconnected the GPIO 8 from the system and began using GPIO 11 instead. It works much more better, but not perfectly yet.

Now the transfers work most of the time, but sometimes (approx. 1 / 2800 transfers) the EDMA does not react to the events leading finally into a missed event.

I give it 16 events through the GPIO 11 pin and it begins to do the transfers, but then it suddenly stops doing them any more. See the oscilloscope screenshot below.

The yellow line is the CS1 showing the reads from EMIF16 to DDR3.

The white line below it shows the events from the GPIO 11 triggering the EDMA.

The blue line below it indicates successful EDMA TCC interrupt.

As seen in the image, the first transfers succeeds OK, but then during the next transfer the EDMA becomes blind for the GPIO 11 events. By using the emulator and stopping into that erroneous status, I can still successfully give SW events by writing into the ESR register. I cannot see any errors active in the EDMA registers either.

I have tried reducing the event frequency --> no effect. I have also checked the GPIO 11 pulse lengths that they are long enough (> 100 ns) and there have never been any difference in them in the successful case vs. failure.

I am lost, but I try to invent ways to debug it more deeply.

Best regards,

Ari

Processors

Processors forum

Cannot clear EDMA3 synchronization event input from a GPIO pin