Data Sharing across DSP cores and ARM cores in TCI6638K2K

Mahantesh Kothiwale

Dear Experts,

I am using EVM K2K with CCSv6. I have created 8 different CCS projects for 8 DSP cores and 1 CCS project for ARM A15 Quadcore(Running SMP TI-RTOS, not linux). Totally 9 projects.

I want to know:

Sharing Data:

- How to make shared memory area between all 9 projects. Both in MSMC SRAM and external DDR3 RAM.

(I learnt that it is possible by setting the MSMC MPAX registers for ARM and DSP cores to map 32-bit addresses to any of the Physical addresses(40-bit space))

After setting MPAX registers, how to access the shared data in the code ..? Can we make special data sections in linked command files and make arrays, structures locate to those data sections (using #pragma) ..?

Please point me to the relevant example code in PDK, which does both MPAX register settings and uses liker command file.

Loading and running all 9 binaries together:

- Currently I can make sngle Target Configuration in CCS to select all 9 cores and select their relevant GEL files. While launching this Target Configuration in CCS, it allows to load all binaries one after another manually.

I want to know, If there is any automatic scripting possible, which runs and loads all binaries by itself and all binaries in their respective cores stop at their main().

Also, want to know, when we dont want to use CCS for loading binaries, and use ROM boot to load our set of binaries from NAND/NOR flash.

- How to combine the binaries as single Image understandable (may be combine in Blob format wIth GP header,...?) by ROM boot . Please point to the relevant tools/scripts for the same.

Thanks,

Mahantesh.

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi Mahantesh,
Thank you for the post. We will get back to you as soon as possible.

0 Mahantesh Kothiwale over 9 years ago in reply to Raja

Prodigy 200 points

Dear Rajasekaran,

Thank you ..

Pls let me know if answers for the queries are available..
Thanks,
Mahantesh

0 Naoki Kawada over 9 years ago in reply to Mahantesh Kothiwale

Guru 19890 points

This is just for your information about automatic scripting.
Go to processors.wiki.ti.com/.../CCS_Modules_Library and you will find a presentation and example code for DSS.
Also, you can find some example scripts at C:\ti\ccsv6\ccs_base\scripting\examples\DebugServerExamples.

Good luck.
Naoki

0 Mahantesh Kothiwale over 9 years ago in reply to Naoki Kawada

Prodigy 200 points

Dear Naoki,

Thank you very much for info on automatic scripting..

Can anybody please help me with the queries related to shared memory ..?

Sharing Data:

- How to make shared memory area between projects of different DSP cores. (In both Both in MSMC SRAM and external DDR3 RAM area).

(I learnt that it is possible by setting the MSMC MPAX registers for ARM and DSP cores to map 32-bit addresses to any of the Physical addresses(40-bit space))

After setting MPAX registers, how to access the shared data in the code ..? Can we make special data sections in linked command files and make arrays, structures locate to those data sections (using #pragma) ..?

Please point me to the relevant example code in PDK, which does both MPAX register settings and uses liker command file.

Thanks,
Mahantesh.

0 ran35366 over 9 years ago in reply to Naoki Kawada

TI__Genius 12805 points

Mahantesh

First a comment - I personally prefer to have one execution with a switch for each core - that is,

"if coreNumber == 0 ) call function0" if core number is 1 call function 1 and so on and so forth

Now to the question that was not answered (I think)

If I understand correctly you want each core to have private memory, and some area for shared memory between all the cores. If you search MPAX in e2e you will find many posting how to use and manage MPAX registers. In particular, if you need to set the MPAX registers before main starts, (for example when there is memory allocation before main()) there is a way to define a startup function in the RTSC cfg file that will configure the MPAX registers before anything else.

While the DSP access using the MPAX is well described in e2e posting, the ARM access is a little different. EDMA access initiated by the ARM will use MPAX set 8 to access SEM and SES but the ARM itself uses the MMU. My suggestion - use the default setting for the ARM (the first 2G of the external memory), use part of it as shared memory, and modify the MPAX of the DSP cores to use higher addresses of the DDR.

One more comment - I never change the default values of the first MPAX registers. I just add higher registers. When the same logical address is mapped to two different physical addresses, the hardware takes the MPAX with the higher index. Thus for your case (If I understand it correctly) you will add two new registers for each DSP core - one for the private memory, and one for the shared memory

Please get back to the posting if you need more information but do search on MPAX in e2e. There are many potings

Ran

0 Mahantesh Kothiwale over 9 years ago in reply to ran35366

Prodigy 200 points

Dear Ran,

Thank you very much for providing insight on MPAX settings to share DDR RAM between ARM and DSP cores.
Yes, your understanding about what I want to do is corrrect.
Just more details on our requirement:
- Each core (8 DSP and 1 SMP Quadcore A15)
Will have shared space of equal size out of their individual 32 bit addresss space..
- Each core will have their private area in 32 bit address space
- ARM Quadcore need not use MMU. We may run TI RTOS SMP on A15
- Want to define the project specific data sections(shared and private)in linker cmd files of each core's project, and use them with #pragma in source code.
As you suggested, will explore the e2e postings of MPAX settings, will try to set registers as per our requirement.

Meanwhile can you suggest, is it recommended to disable MMU for ARM and use MPAX to convert ARM 32 bit to Physical address ?

Thanks for your help,
Mahantesh..

0 Mahantesh Kothiwale over 9 years ago in reply to ran35366

Prodigy 200 points

Dear Ran,

I am able to share the data in DDR3 (first 2GB) and MSMC SRAM across 2 DSP core.

I defined my .xdt file in CCS project to add my data sections:

MySections.xdt will contain:

.gdataddr: load >> DDR3
.gdatamsmc: load >> MSMCSRAM
.gdatal2sram: load >> L2SRAM
`$args[1]`

While building project in CCS, xdc tools will generate Linker.com with the above sections from .xdt files.
Linked.cmd after build:

SECTIONS
{
.gdataddr: load >> DDR3
.gdatamsmc: load >> MSMCSRAM
.gdatal2sram: load >> L2SRAM
......
......
......
}

In .c file of my code, I used #pragma to define global arrays..

struct shared_DDR3 {
int flag;
int arrayy[10];
};

struct shared_MSMC {
int flag;
int arrayy[10];
};

struct shared_L2SRAM {
int flag;
int arrayy[10];
};

#pragma DATA_SECTION(shared_DDR3_data, ".gdataddr")
struct shared_DDR3 shared_DDR3_data;

#pragma DATA_SECTION(shared_MSMC_data, ".gdatamsmc")
struct shared_MSMC shared_MSMC_data;

These global structures gets allocated as per sections mentioned in #pragma directive statement.
After replicating the same in another DSP core project, and run both core project together, these structures are shared in memory.

Just wondering how to add new MEMORY areas as well in Linker.cmd like we can add new SECTIONS using .xdt file.
default memory area in Linker.cmd

MEMORY
{
L2SRAM (RWX) : org = 0x800000, len = 0x100000
MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
DDR3 : org = 0x80000000, len = 0x80000000
}

How to add new MEMORY component ? Please let me know if anybody has done this ...

Thanks,
Mahantesh.

0 ran35366 over 9 years ago in reply to Mahantesh Kothiwale

TI__Genius 12805 points

There are two ways to define new memory segment (I think that this is what you ask)

If the project is not RTSC project, that is, if there is not cfg file, then you modify the linker command file. Just remember that you cannot have two memory segment with overlapping addresses

For a RTSC project you have to define a private platform. To do so you first have to find the directory where the platform that you use is located. Enclosed is a document that I wrote a long time ago that describes how to define a new platform

Ran/cfs-file/__key/communityserver-discussions-components-files/791/6747.defineCustomerPlatform.docx

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Data Sharing across DSP cores and ARM cores in TCI6638K2K