Happy new year all,
We are building our own board based on C6678L EVM
As discussed in: "e2e.ti.com/.../160635"
The bootmode is fed to DSP from FPGA . The IBL Init reads this info from the FPGA via SPI interface .The initial boot is foced to I2C @ 0x51 by FPGA to take care of PLL workaround.
In my application, we are only using: IBL NOR boot on image 0.
Can we design our board WITHOUT the DIP SWITCHES and force our "IBL NOR boot on image 0" by hard coding the SPI Reply to BM GPIO STATUS in the FPGA code?
Here is where this is done:
shevm_fpga_core (lines 1027, 1028)
spi_reg[39:32] <= bm_gpio[7:0]; // 8'h4: BM GPIO (RO)
spi_reg[47:40] <= bm_gpio[15:8];
shevm_fpga_core (lines 1161)
bm_gpio[15:0] <= bm_gpio_i[15:0]; //DC switch with 1 sync should be OK
So, hard coding bm_gpio[15:0] should eliminate the need for the DIP SWITCHES....We are not planning to use another bootmode...
-if we do so, will be able to connect to the C6678 using the JTAG (No Boot)...if not, we can use 1 DIP SWITCH to select between the two modes!?
Regards,
Murad
