Hi all,
I'm trying to understand the effects of a division by zero on the DSP. According to
my previous post (https://e2e.ti.com/support/embedded/tirtos/f/355/t/573031), there
are three registers (FADCR, FAUCR, FMCR) which should set up a bit when the division by zero happens. In
particular, the INFO bit should be set.
Unfortunately no bit sets up. I inspected every register and I didn't find any changes.
I couldn't notice any bit changes.
Please, can anybody help me understand which bit to read?
Giovambattista Astorino