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66AK2G02: Connection of unused balls - conflicts between K2G EVM and datasheet

Debora
Intellectual 645 points
Part Number: 66AK2G02
Other Parts Discussed in Thread: OMAP-L137,

Section 4.5 of the datasheet, "Connections for Unused Pins", has some very cumbersome requirements for individual pullup or pulldown resistors on many pins when unused. The K2G EVM doesn't adhere to these requirements, so it appears that they are not really required.

The datasheet says 

AC19 / L4 / AD1 / AD4 / AE6 / AE9 / M2 / N4 / M1 / M3 / N2 / P2 / N1 / P1 / T4 / T1 / D24 / C17 / L5 / AC25 / AD24 / L21 / L23

Each of these balls must be connected to GND through a separate external pull resistor if unused

Is this really true?  For example, on the EVM SPI0_CLK, SPI0_SIMO, SPI_SOMI, and SPI0_SCSn0 (M2 / N4 / M1 / M3) are connected to an expansion header with no pulldowns on the EVM.  This is an apparent violation of the datasheet requirement.  And on the EVM RMII_REFCLK (D24) is connected to a test point with no pulldown, in apparent violation of the requirement.

I am surprised that TDI (L5) requires a pulldown, because it has not needed one on previous processors according to the XDS Target Connection Guide.

The datasheet also says 

L3 / W1 / W3 / K4 / AE2 / AE4 / AD6 / AD9 / U5 / W5 / V6 / W4 / V5 / V4 / AD25 / AE24 / K21 / M23 

These balls must be connected to the corresponding power supply through a separate external pull resistor if unused

Again, I am surprised that TCK (L3) and TMS (K4) require pullups, because they have not previously needed them according to the XDS Target Connection Guide.

Then the datasheet notes 

The following balls are reserved: Y1 (RSV13) / AA1 (RSV14) / AB1 (RSV15) / AA2 (RSV16) / AB2 (RSV17) / AC1 (RSV18)
These balls must be connected to DVDD18 through a separate external pull resistor.

However in the K2GEVM schematic they are connected to test points or to non-stuffed resistors. Are they required to be connected to DVDD18 or not?

Then the datasheet notes

All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused signal balls should only be connected to a pad on the PCB. No trace or via should be connected to the pad for an unused signal. If trace or a via is connected to an unused signal pad, an external pulling resistor is required. Failure to included an external resistor could result in a high current state which could damaged the IO cell.

Seriously? I haven't looked at these exhaustively, but one example I see in the EVM schematic is K2, which is connected to a test point and has no external pulling resistor.

  • 0
    Intellectual 645 points
    I continue to be perplexed as I look through more documents because SPRAC54, the 66AKG202 Schematic Checklist, gives a different rule.

    Signals on unused interfaces can typically be left as no connect. Check the Pin Attributes table to determine if the unused pin has an internal pulling resistor during reset. If the pin does not have an internal pulling resistor active during reset, an external pulling resistor should always be included in the design. If present, the internal pulling resistor holds the unused pin in a known state, provided no external connection is made to the pin. If any trace or via is connected to the pad for an unused pin, an external pulling resistor must be included in the design. This includes test points, test headers, and dogbone connections for a fully populated CAD footprint.

    In my design I am connecting a 16-bit wide DDR3L. My unused DDR signals include
    DDR3_CBDQS_P/N
    DDR3_DQM2/ 3 and DDR3_CBDQM
    DDR3_CB00/1/2/3
    DDR3_CLKOUT_P1/N1

    All of these are listed in datasheet table 4-28, so that means they have a Pad Configuration Register and they therefore CAN be left unconnected according to the rule in section 4-29 of the datasheet.

    However, none of them have a pulling resistor during reset according to Table 4-1. Thus, according to the rule in the schematic checklist, they CANNOT be left unconnected and require an external pulling resistor.

    Since the two documents contradict each other, which is correct? (DDR3_CLKOUT_P1 and DDR3_CLKOUT_N1 are left unconnected in the K2G EVM, suggesting that resistors are not needed.)

    DDR3_ODT1, DDR3_CKE1, and DDR3_CEn1 are connected to test points in the EVM. Is this permitted? It seems to contradict the documents, both of which forbid test points.

    As for AD24, AE24, AE6, AD6, AE9, and AD9, they are specifically mentioned in table 4-29, so they are explicitly required to have an external pull resistor. Can you recommend a value for these external pull resistors?

    It doesn't seem logical that AE6, AD6, AE9, and AD9 (DDR3_DQS2_ P/N and DDR3_DQS3_P/N) would be mentioned in table 4-29 as requiring special treatment, but AE12 and AD12 (DDR3_CBDQS_P/N) are not called out. Why is there a difference between these data strobes?
  • 0 in reply to Debora
    TI__Guru 65405 points
    Hi Debora,

    I've forwarded this to the design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Debora
    TI__Guru**** 161600 points
    Hi Debora,
    1)
    All of these are listed in datasheet table 4-28, so that means they have a Pad Configuration Register and they therefore CAN be left unconnected according to the rule in section 4-29 of the datasheet.

    This is NOT correct. If you have a look at table 4-28 in the data manual, you'll see that there is NO register name associated with the ddr pins. This means that they do NOT have associated Pad Configuration Register.
    So these follow under the recommendation given in 4.5 Connections for Unused Pins:
    "NOTE
    All other unused signal balls without Pad Configuration Register can be left unconnected."

    However, I think there is something missing in the Data Manual (I am checking this with the documentation team).. The DQS & CLKOUT signals, which are differential signals should be tied (to ground or power supply) as described in the Schematic Checklist. I will check this further and elaborate here.

    2)
    It doesn't seem logical that AE6, AD6, AE9, and AD9 (DDR3_DQS2_ P/N and DDR3_DQS3_P/N) would be mentioned in table 4-29 as requiring special treatment, but AE12 and AD12 (DDR3_CBDQS_P/N) are not called out. Why is there a difference between these data strobes?


    For the differential clock out input, I think you need to follow 3.3 Unused Clock Inputs from Hardware design guide for keystone II devices (www.ti.com/.../sprabv0.pdf). See also 6.8.3 Unused DDR3 Pin Requirement from the same document. Again I will verify this and elaborate furhter.

    3) As for recommended values for the external pull resistors for AD24, AE24, AE6, AD6, AE9, and AD9, you can use:
    In my experience you should be fine with standard values: 1 KOhm, 4.7 KOhm or 10 KOhm.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 645 points

    Hi Yordan,

    Thanks for looking into the DDRs.  Any comment on the questions in my first post?  

    On the EVM SPI0_CLK, SPI0_SIMO, SPI_SOMI, and SPI0_SCSn0 (M2 / N4 / M1 / M3) are connected to an expansion header with no pulldowns on the EVM.  And on the EVM RMII_REFCLK (D24) is connected to a test point with no pulldown.  This is an apparent violation of the requirement in table 4-29 of the datasheet  

    Do TCK (L3) and TMS (K4) really need pull resistors (Table 4-29)?  They didn't need them in previous SoCs such as the OMAP-L137 and aren't shown in the  XDS Target Connection Guide.

    What about "Y1 (RSV13) / AA1 (RSV14) / AB1 (RSV15) / AA2 (RSV16) / AB2 (RSV17) / AC1 (RSV18)  These balls must be connected to DVDD18 through a separate external pull resistor." On the EVM these balls have no pull resistor.  Do I really need to add pull resistors?

    What about the rule "Unused signal balls should only be connected to a pad on the PCB. No trace or via should be connected to the pad for an unused signal. If trace or a via is connected to an unused signal pad, an external pulling resistor is required. Failure to included an external resistor could result in a high current state which could damaged the IO cell."  On the EVM K2, for example, is connected to a test point and does not have a pull resistor.  Do I really need to add pull resistors? Basically, the question is why are the I/O pads on the 66AK2G02 so sensitive that they require external pull resistors on unused GPIO pins that are connected to a via or test point etc.?  This is an onerous rule and the K2G EVM does not folllow it.

    Regards,

    Debora

  • 0 in reply to Debora
    TI__Guru**** 161600 points
    Hi,

    Let me have a look at all these and I'll get back to the thread with my findings.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 645 points
    Hi Yordan,

    Thank you. Awaiting your follow-up both on the DDR pins and on the general pins.

    By the way, regarding what you said about the DDR pins, " If you have a look at table 4-28 in the data manual, you'll see that there is NO register name associated with the ddr pins..." the documentation team might want to fix table 4-28 in SPRS923D. The "Register Name" column (and almost every other column) is blank for every ball.

    Regards,
    Debora
  • 0 in reply to Debora
    TI__Mastermind 42545 points
    Hi Debora,
    The EVM for this part was designed before we received the first silicon device and the final documentation. We strive to design to what we think the final recommendations should be but sometimes we don't catch everything. In addition, there are also signals that are not used on customer boards but are needed for internal use which are often routed to test points. The data manual includes all the final recommendations from the design team and it should be followed for all board designs.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Prodigy 10 points

    We're looking at a lot of unused pins in some of the designs we will have.

    I'm not clear as to why, if there's an issue with just relying on the built in PU/PD capability to avoid them floating, they can't just be tied to ground? It kind of reads like there's some concern about current limiting with the per pin R?

  • 0 in reply to Brewster
    TI__Mastermind 42545 points
    Hi Brewster,
    There is a specific list of signals that need to be externally terminated. This is a subset of the IO pins available. As stated in the data manual, all other unused signal balls with a pad configuration register can be left unconnected with their multiplexing mode set to GPIO input and internal pull down resistor enabled. These signals should not have any trace attached to the pads.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Intellectual 645 points
    Hi Bill,

    Sorry for being dense. I am still confused as to why unused GPIOs need external pulldowns if they're brought out to a header or test point. "All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled. Unused signal balls should only be connected to a pad on the PCB... If trace or a via is connected to an unused signal pad, an external pulling resistor is required. Failure to included an external resistor could result in a high current state which could damaged the IO cell"

    I don't really understand the spirit of this rule. Why can't they be set to GPIO output and not have an external pulldown?

    What about pins such as E21 and D21? Suppose I intend them to be UART pins and the software configures them as such after boot, but I bring them to an external connector which might or not be connected. Do they become "unused" for the purposes of the rule and therefore require pulldowns if nothing is connected to the connector?

    I certainly understand why unused LVDS inputs need resistors. I just don't have my mind around the GPIOs yet.

    Regards,
    Debora
  • 0 in reply to Debora
    TI__Mastermind 42545 points
    Hi Debora,
    I'm sorry if this is confusing. For our purposes, unused pins are pins without any configuration by the user. Most of the pins on the device will default to GPIO inputs with an internal pulling resistor enabled. That internal pulling resistor is designed to hold the pin in a stable state if nothing is connected to the ball. This is important since a mid-level voltage on an input pin will result in higher leakage current at the ball. To avoid this added current, unused pins that are left in an input state should be held in either a stable high or low state. The internal pulling resistor is sufficient to achieve this if nothing is connected to the pin on the PCB but we can't guarantee that it will be sufficient if an external connection is present. We recommend that unused pins with an external connection also include an external pulling resistor to maintain a stable state and avoid addition current. If you are configuring a pin as an output, it is no longer considered unused but there may be some additional current draw until the configuration is done.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Intellectual 645 points

    Hi Bill,

    Thanks, that helps a lot.

    Can you clarify the requirement in Table 4-29 for balls T4 and T1?  They are required to have external pulldowns if unused. I am unsure about what "unused" means in this context because according to Table 4-1 they have only one function, UART0_RXD and UART0_TXD and are configured to muxmode 0 on reset release. They have pullups during reset, so it seems to me that the pullups would conflict with the required pulldowns and pull them to a mid-voltage state.

    Regards,

    Debora

  • 0 in reply to Debora
    Intellectual 645 points
    Hi Bill,

    Any word yet on the apparent conflict between the required pulldowns on T4 and T1 versus the internal pullups during reset? I'm finalizing my design.

    Regards,
    Debora