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66AK2L06: 66AK2L06

chihjay chang
Prodigy 30 points
Part Number: 66AK2L06
Other Parts Discussed in Thread: RFSDK, TCI6630K2L, ADC32RF80, DAC38J84

1. The SPRS930 specify DFE nominal maximum frequency is 368.64 MHz, therefore in SPRY293 it claims it could process 736 MHZ real data as 368 MHZ IQ inputs. However, from the SPRUHX8A document it states that the RX Output Formatter from the RX Sub-block will interleave IQ data and the DDUC process IQ data as interleaved format(page 41,2.3.1). Is that means it take at least two DFE cycles for a pair of IQ so the maximum input rate is actually restricted to 184MHZ for IQ hence 368MHZ as real data?

2. Can DFE PLL could be configured as different rate other than 368.64 or 245.76M?

3. What type of the filter the F1, F2 decimators in RX block are? How can we configure F1 and F2? (no related API mentioned in 2.10.6) Can they be adjusted or it has the fixed pass band that will cut-off fixed bandwidth?

4. In 2.6.1 it mentioned CDFR has 4 output streams has a unique parallel IQ DPD output stream. What exactly are these four streams? From the following block diagram it shows that each stream of the 4 are all combination of 1 or 2 IQ interleaved TX stream, so they shout the same antenna combination TX stream in the set of two. Are they from the pre/post-CFR sub function block of the CFR?

5. It mentioned about hardware register setup for some DFE function block. Is there any document contain register map list?

6. Where can I find the API manual for DFE API setting?

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the Radar team. Their feedback will be posted directly here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 30 points

    Thank you very much, Yordan

    By the way, we would also like to know if  the 66AK2L06 is able to support for measuring 160MHz occupied bandwidth ?

  • 0 in reply to chihjay chang
    TI__Mastermind 37500 points

    Hello, Trying to Answer the first two questions, and then the added question.

    a) The DFE PLL, and SYSREF Logic block programming is supported for a DFE usage rate of 245.76Mhz (PLL 983.04Mhz) and 368.64Mhz (PLL 737.28Mhz).

       The RFSDK which can be requested as one of the tools has examples and programming for IQNet, DFE, the DFEPLL and Sysref Logic, and Serdes.

    b) There is both Tx and Rx that can be configured for processing.  In most cases, customers select a radio select, use case from the RFSDK, and develop their application.  There are third party developers that can add the use cases for software support.

    c) The JESD serdes supports upto 7.3828Gbps for DFE, which has either special lane processing for 1 Rx as real samples split across two lanes.   The ADC output sample rate is 737.28Msps, output as 2 lanes of odd and even at 368.64Msps.   The Rx block has a special format for converting 737.28Msps real to 368.64Msps complex using the Rx-R2C block.

    This is discussed in the DFE User Guide which can be downloaded from the TCI6630K2L or 66AK2L06 web page.   Note: implementation in the RFDSK, is not a standard project for real odd,even.   There are examples of using the design 1, or design4 adjacent market designs that have 368.64Msps complex sample rate.

    d) related to 160Msps occupied bandwidth.   The DFE communicates with IQN for baseband data.  In the design 4 adjacement market design, you can find reference

    under the 66Ak2L06, using the DAC38J84, and ADC32RF80, there is special processing for 1 complex stream at 368.64Msps constructed of two baseband carriers 92.16Msps IQ rate, these two carriers are mixed and summed into the 368.64Msps complex rate.   

    While there is NOT a baseband IQ rate of 160Msps, if you can spread your signals of interested across two 70Mhz IQ carriers, for Tx, and two for Rx.  You can try this with the JESD lane loopback, 66AK2L06 EVM, and the RFSDK.

    -  (Design 4 reference) www.ti.com/.../tidep0081

    Regards,

    Joe Quintal

  • 0 in reply to Radio-Joe
    Prodigy 30 points

    Thank you for your reply

    and yes, we had already study the content of tidu946a and thinking that the structure is not able to meet our requirement of occupied bandwidth of 160MHZ (the design is 150MHZ in computational at Max)

    We also looking forward to the answers of other questions; your immediate response on this matter is highly appreciated.