TMS320TCI6614: DDR3 clock duty cycle adjustable

Tony Tang

Part Number: TMS320TCI6614

is the DDR3 clock duty cycle adjustable?

Customer have some boards not stable, measured the DDR clock duty cycle found it is a little big, up to 57%, and it lead to read DQS duty cycle also up to 58%. Ask whether the clock duty cycle adjustable from register?

Customer monitor the DDR_CLK found the duty cycle changing during booting, seems it related to DDR initialization.

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi Tony,

I've forwarded this to the hardware design experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 Bill Taboada over 8 years ago

TI__Mastermind 42545 points

Hi Tony,

Are we discussing the DDR reference clock or the DDR clock connected to the memories?

Regards,

Bill

0 Tony Tang over 8 years ago in reply to Bill Taboada

TI__Mastermind 29152 points

Bill,

The DDR clock connected to the memories.

0 Bill Taboada over 8 years ago in reply to Tony Tang

TI__Mastermind 42545 points

Hi Tony,

The duty cycle requirement of the clock and defined by JESD79-3F and the TCI6614 is designed to meet that specification. No adjustment to the duty cycle should be needed for proper operation of the DDR3 interface. If you are experiencing problems check that the jitter requirements for the reference clock and the routing requirements have been met. Does the interface fail if you slow the speed of the DDR3 interface?

Regards,

Bill

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TMS320TCI6614: DDR3 clock duty cycle adjustable