CCS/K2GICE: Gigabit eth port does not work in CCS debug mode with NDK example

Hi,

The user guide clearly says:
Apply +24 V to the K2G ICE with either a bench power supply or with a +24-V power supply purchased separately, as shown in Figure 5.

Yes this could be a problem when booting your board.

Best Regards,
Yordan

Thank you for your reply.

However, the user guide document(spruie3, section 1.5 power supply) says that a +12v adapter is also available.

----

The K2G ICE can be powered from one of two sources: a single external power supply connected to the
DC power jack (J6), or the 12-V supply pins on the PCIE edge connector. The power supply circuit is
designed to allow the use of either a +24-V / 2.5-A DC (60-W) external power supply or a +12-V / 5-A DC
(60-W) external power supply.

----

BTW, I plugged in the 24v adapter, but the gigabit port still does not work.

The fast ethernet ports blink when the cable is plugged in, but the gigabit port's led does not respond when the cable is plugged in.

Hi,

Do you run any GEL file to initialize the K2G SOC before load and run the EMAC example?

Regards, Eric

To lding,

Of course!! I ran the icek2g_arm.gel file before running scripts related to EMAC.

pdk k2g 1.0.8, processor_sdk_rtos_k2g_4.2.0

icek2g_arm.gel

----

CortexA15: GEL Output: K2G ICE EVM Setup is in Progress...

CortexA15: GEL Output: Power on all PSC modules and power domains...

CortexA15: GEL Output: Power on PSC modules and power domains... Done.

CortexA15: GEL Output: K2G ICE EVM PLL Setup is in Progress...

CortexA15: GEL Output: External Clock Mode

CortexA15: GEL Output: C66x PLL has been configured (25.0 MHz * 96 / 1 / 4 = 600.0 MHz)

CortexA15: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (25.0 MHz * 96 / 1 / 4 = 600.0 MHz)

CortexA15: GEL Output: UART PLL has been configured (25.0 MHz * 767 / 5 / 10 = 383.5 MHz)

CortexA15: GEL Output: NSS PLL has been configured (25.0 MHz * 240 / 3 / 2 = 1000.0 MHz)

CortexA15: GEL Output: ICSS PLL has been configured (25.0 MHz * 240 / 3 / 10 = 200.0 MHz)

CortexA15: GEL Output: DDR PLL has been configured (25.0 MHz * 128 / 1 / 16 = 200.0 MHz)

CortexA15: GEL Output: XMC setup complete.

CortexA15: GEL Output: DDR3 PLL Setup ...

CortexA15: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.

CortexA15: GEL Output: DDR3A initialization complete

CortexA15: GEL Output: K2G ICE EVM PLL Setup is Done!

CortexA15: GEL Output: Entering A15 non secure mode ..

CortexA15: GEL Output: Enabling non-secure access to cp10 and cp11

CortexA15: GEL Output: Enabled non-secure access to cp10 and cp11

CortexA15: GEL Output: Making all GIC interrupts Group1

CortexA15: GEL Output: Changed interrupt group

CortexA15: GEL Output: Set secure mode PMR to non-zero value

CortexA15: GEL Output: Entering NonSecure Mode

CortexA15: GEL Output: Entered NonSecure Mode

CortexA15: GEL Output: A15 non secure mode entered

CortexA15: GEL Output: K2G ICE EVM Setup is Done!

----

ICSS0 EthPHY0 Register Read script result

CortexA15: GEL Output: PRU0 MDIO is enabled

CortexA15: GEL Output: PRU0 MDIO pinmux is enabled

CortexA15: GEL Output: PRU0 MDIO PHY0 settings are as follows

CortexA15: GEL Output: PHY REG 0x00000000 = 0x00003100

CortexA15: GEL Output: PHY REG 0x00000001 = 0x00007849

CortexA15: GEL Output: PHY REG 0x00000002 = 0x00002000

CortexA15: GEL Output: PHY REG 0x00000003 = 0x0000A240

CortexA15: GEL Output: PHY REG 0x00000004 = 0x000001E1

CortexA15: GEL Output: PHY REG 0x00000005 = 0x00000000

CortexA15: GEL Output: PHY REG 0x00000006 = 0x00000004

CortexA15: GEL Output: PHY REG 0x00000007 = 0x00002001

CortexA15: GEL Output: PHY REG 0x00000008 = 0x00000000

CortexA15: GEL Output: PHY REG 0x00000009 = 0x00000000

CortexA15: GEL Output: PHY REG 0x0000000A = 0x00000100

CortexA15: GEL Output: PHY REG 0x0000000B = 0x00001000

CortexA15: GEL Output: PHY REG 0x0000000C = 0x00000000

CortexA15: GEL Output: PHY REG 0x0000000D = 0x00000000

CortexA15: GEL Output: PHY REG 0x0000000E = 0x00000000

CortexA15: GEL Output: PHY REG 0x0000000F = 0x00000000

CortexA15: GEL Output: PRU0 MDIO PHY0 Boot strap settings are as follows

CortexA15: GEL Output: PHY REG 0x00000467 = 0x000003CF

CortexA15: GEL Output: PHY REG 0x00000468 = 0x00000000

---------------

but,  Eth0PHY Register Read Script result is

CortexA15: GEL Output: MDIO is enabled

CortexA15: GEL Output: MDIO pinmux is enabled

CortexA15: GEL Output: Gig Eth MDIO PHY settings are as follows

CortexA15: GEL Output: PHY REG 0x00000000 read fail

CortexA15: GEL Output: PHY REG 0x00000001 read fail

CortexA15: GEL Output: PHY REG 0x00000002 read fail

CortexA15: GEL Output: PHY REG 0x00000003 read fail

CortexA15: GEL Output: PHY REG 0x00000004 read fail

CortexA15: GEL Output: PHY REG 0x00000005 read fail

CortexA15: GEL Output: PHY REG 0x00000006 read fail

CortexA15: GEL Output: PHY REG 0x00000007 read fail

CortexA15: GEL Output: PHY REG 0x00000008 read fail

CortexA15: GEL Output: PHY REG 0x00000009 read fail

CortexA15: GEL Output: PHY REG 0x0000000A read fail

CortexA15: GEL Output: PHY REG 0x0000000B read fail

CortexA15: GEL Output: PHY REG 0x0000000C read fail

CortexA15: GEL Output: PHY REG 0x0000000D read fail

CortexA15: GEL Output: PHY REG 0x0000000E read fail

CortexA15: GEL Output: PHY REG 0x0000000F read fail

CortexA15: GEL Output: PHY REG 0x0000006E read fail

CortexA15: GEL Output:  Gig Eth PHY0 Boot strap settings are as follows

CortexA15: GEL Output: PHY REG 0x0000006E read fail

In debug mode, the register values are as follows.

The script input the MDIO init value, but it failed to init the value (Fault indicator bit set to 1).

#define MDIO_CTL *(unsigned int*)(0x4200F00 + 0x04)
#define MDIO_PHY_REG *(unsigned int*)(0x4200F00 + 0x80)

#define PADCONFIG98 *(unsigned int*)(CHIP_LEVEL_REG + 0x1188)
#define PADCONFIG99 *(unsigned int*)(CHIP_LEVEL_REG + 0x118C)

MDIO_Init()
{
MDIO_CTL = 0x411400ff;
GEL_TextOut( "MDIO is enabled\n");
//MDIO_CLK_PADCONFIG= DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_00, DEVICE_PIN_MUX_RX_DISABLED, DEVICE_PIN_MUX_PULL_UP, DEVICE_PIN_MUX_PULL_ENABLE, DEVICE_PIN_MUX_MODE_PRIMARY)
PADCONFIG98 = 0x00060000;
//MDIO_DATA_PADCONFIG= DEVICE_PIN_MUX_VALUE (DEVICE_PIN_MUX_BUFFER_CLASS_00, DEVICE_PIN_MUX_RX_ENABLED, DEVICE_PIN_MUX_PULL_UP, DEVICE_PIN_MUX_PULL_ENABLE, DEVICE_PIN_MUX_MODE_PRIMARY)
PADCONFIG99 = 0x00020000;

GEL_TextOut( "MDIO pinmux is enabled\n");
}

In user guide, file name SPRUIE3, section 2.9.3 Gigabit Ethernet configuration

There are some register settings for using Gigabit Ethernet, but it seems that the initialization in the gel file does not work properly.

Hi,

Let me find a K2G ICE board and test it.

Regards, Eric

Eric,

I'm sorry to bother you, but are you still checking?

Hi,

Sorry for the late! I tried the same K2G 1.0.8 EMAC example on the ICE K2G board, I don't have any issue. The test passed.

For the GEL:
CortexA15: GEL Output: K2G ICE EVM Setup is in Progress...

CortexA15: GEL Output: Power on all PSC modules and power domains...
CortexA15: GEL Output: Power on PSC modules and power domains... Done.

CortexA15: GEL Output: K2G ICE EVM PLL Setup is in Progress...

CortexA15: GEL Output: Internal Clock Mode
CortexA15: GEL Output: C66x PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz)
CortexA15: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz)
CortexA15: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz)
CortexA15: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz)
CortexA15: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz)
CortexA15: GEL Output: DDR PLL has been configured (24.0 MHz * 133 / 1 / 16 = 199.5 MHz)
CortexA15: GEL Output: XMC setup complete.
CortexA15: GEL Output: DDR3 PLL Setup ...
CortexA15: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.
CortexA15: GEL Output: DDR3A initialization complete
CortexA15: GEL Output: K2G ICE EVM PLL Setup is Done!

CortexA15: GEL Output: Entering A15 non secure mode ..
CortexA15: GEL Output: Enabling non-secure access to cp10 and cp11
CortexA15: GEL Output: Enabled non-secure access to cp10 and cp11
CortexA15: GEL Output: Making all GIC interrupts Group1
CortexA15: GEL Output: Changed interrupt group
CortexA15: GEL Output: Set secure mode PMR to non-zero value
CortexA15: GEL Output: Entering NonSecure Mode
CortexA15: GEL Output: Entered NonSecure Mode
CortexA15: GEL Output: A15 non secure mode entered

CortexA15: GEL Output: K2G ICE EVM Setup is Done!

CortexA15: GEL Output: MDIO is enabled
CortexA15: GEL Output: MDIO pinmux is enabled
CortexA15: GEL Output: Gig Eth MDIO PHY settings are as follows
CortexA15: GEL Output: PHY REG 0x00000000 = 0x00001140
CortexA15: GEL Output: PHY REG 0x00000001 = 0x00007949
CortexA15: GEL Output: PHY REG 0x00000002 = 0x00002000
CortexA15: GEL Output: PHY REG 0x00000003 = 0x0000A231
CortexA15: GEL Output: PHY REG 0x00000004 = 0x000001E1
CortexA15: GEL Output: PHY REG 0x00000005 = 0x00000000
CortexA15: GEL Output: PHY REG 0x00000006 = 0x00000064
CortexA15: GEL Output: PHY REG 0x00000007 = 0x00002001
CortexA15: GEL Output: PHY REG 0x00000008 = 0x00000000
CortexA15: GEL Output: PHY REG 0x00000009 = 0x00000300
CortexA15: GEL Output: PHY REG 0x0000000A = 0x00000000
CortexA15: GEL Output: PHY REG 0x0000000B = 0x00000000
CortexA15: GEL Output: PHY REG 0x0000000C = 0x00000000
CortexA15: GEL Output: PHY REG 0x0000000D = 0x00000000
CortexA15: GEL Output: PHY REG 0x0000000E = 0x00000000
CortexA15: GEL Output: PHY REG 0x0000000F = 0x00003000
CortexA15: GEL Output: PHY REG 0x0000006E = 0x00000000
CortexA15: GEL Output: Gig Eth PHY0 Boot strap settings are as follows
CortexA15: GEL Output: PHY REG 0x0000006E = 0x00002000

I saw you used:
CortexA15: GEL Output: External Clock Mode, this is 25MHz input clock. My test is Internal Clock Mode with
24MHz input clock. Did this cause the issue?

This is determined from BOOTCFG_PLLCLKSEL_STAT (0x262_0720)

0 - HF Oscillator drives the SYSCLK as reference input clock to the
PLLs
1 - SYSCLK_P and SYSCLK_N pins drive the reference input clock
to the PLLs

How you input clock externally? Can you use the onboard clock for test?

Regards, Eric

To Eric,

First, thank you for your reply.

I was confused because I did not know the exact result.

I checked the internal and external clock operation.

Clock selection changed from manual(spruie3.pdf, K2G ICE User's Guide file) to boot mode selection.

Mode1 (internal clock, 24MHz, 0010 0000, J3 short)
Mode2 (external clock, 25MHz, 0100 0000, J3 open)

However, in both cases, the operation is not working properly.

In mode2, the initialization operation results are the same as you.

CortexA15: GEL Output: K2G ICE EVM Setup is in Progress...

CortexA15: GEL Output: Power on all PSC modules and power domains...
CortexA15: GEL Output: Power on PSC modules and power domains... Done.

CortexA15: GEL Output: K2G ICE EVM PLL Setup is in Progress...

CortexA15: GEL Output: Internal Clock Mode
CortexA15: GEL Output: C66x PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz)
CortexA15: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz)
CortexA15: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz)
CortexA15: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz)
CortexA15: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz)
CortexA15: GEL Output: DDR PLL has been configured (24.0 MHz * 133 / 1 / 16 = 199.5 MHz)
CortexA15: GEL Output: XMC setup complete.
CortexA15: GEL Output: DDR3 PLL Setup ...
CortexA15: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.
CortexA15: GEL Output: DDR3A initialization complete
CortexA15: GEL Output: K2G ICE EVM PLL Setup is Done!

CortexA15: GEL Output: Entering A15 non secure mode ..
CortexA15: GEL Output: Enabling non-secure access to cp10 and cp11
CortexA15: GEL Output: Enabled non-secure access to cp10 and cp11
CortexA15: GEL Output: Making all GIC interrupts Group1
CortexA15: GEL Output: Changed interrupt group
CortexA15: GEL Output: Set secure mode PMR to non-zero value
CortexA15: GEL Output: Entering NonSecure Mode
CortexA15: GEL Output: Entered NonSecure Mode
CortexA15: GEL Output: A15 non secure mode entered

CortexA15: GEL Output: K2G ICE EVM Setup is Done!

The results are as follows.

CortexA15: GEL Output: MDIO is enabled
CortexA15: GEL Output: MDIO pinmux is enabled
CortexA15: GEL Output: Gig Eth MDIO PHY settings are as follows
CortexA15: GEL Output: PHY REG 0x00000000 read fail
CortexA15: GEL Output: PHY REG 0x00000001 read fail
CortexA15: GEL Output: PHY REG 0x00000002 read fail
CortexA15: GEL Output: PHY REG 0x00000003 read fail
CortexA15: GEL Output: PHY REG 0x00000004 read fail
CortexA15: GEL Output: PHY REG 0x00000005 read fail
CortexA15: GEL Output: PHY REG 0x00000006 read fail
CortexA15: GEL Output: PHY REG 0x00000007 read fail
CortexA15: GEL Output: PHY REG 0x00000008 read fail
CortexA15: GEL Output: PHY REG 0x00000009 read fail
CortexA15: GEL Output: PHY REG 0x0000000A read fail
CortexA15: GEL Output: PHY REG 0x0000000B read fail
CortexA15: GEL Output: PHY REG 0x0000000C read fail
CortexA15: GEL Output: PHY REG 0x0000000D read fail
CortexA15: GEL Output: PHY REG 0x0000000E read fail
CortexA15: GEL Output: PHY REG 0x0000000F read fail
CortexA15: GEL Output: PHY REG 0x0000006E read fail
CortexA15: GEL Output: Gig Eth PHY0 Boot strap settings are as follows
CortexA15: GEL Output: PHY REG 0x0000006E read fail

Did I make the boot mode selection wrong?

Regards, schezow

Hi,

In your log,

Mode2 (external clock, 25MHz, 0100 0000, J3 open)

However, in both cases, the operation is not working properly.

In mode2, the initialization operation results are the same as you.

CortexA15: GEL Output: K2G ICE EVM Setup is in Progress...

CortexA15: GEL Output: Power on all PSC modules and power domains... 
CortexA15: GEL Output: Power on PSC modules and power domains... Done.

CortexA15: GEL Output: K2G ICE EVM PLL Setup is in Progress...

CortexA15: GEL Output: Internal Clock Mode

How you have external clock setup (mode 2) but GEL showed internal clock mode? What is the result with J3 short? From EVM user guide, "Select the 24-MHz crystal as the clock source for the K2G by shorting the pins jumper J3, using the shunt provided, as shown in Figure 3. The K2G ICE should be delivered with the shunt installed."

My test was based on J3 short for on-board clock.

Regards, Eric

 

To Eric,

Of course, mode 2 operates as an external clock. In the previous article, mode 2 is used as an external clock.

The log also says it uses an external clock.

I mean that modes 1 and 2 do not work properly regardless of internal or external clock behavior.

In other words, when mode 1 is selected, it operates as an internal clock, and when mode 2 is selected, it operates as an external clock.

In both cases, however, phy reading does not work.

Regards, schezow