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CCS/66AK2H14: Hyperlink is not working in non loopback mode

mahima shanbag
Expert 1585 points

Part Number: 66AK2H14

Tool/software: Code Composer Studio

Hi,

We have designed  customized  board  using 66AK2H14. We are using CCSV7.4,processor_sdk_rtos_k2hk_4_03_00_05 and TI XDS 110 debug probe to connect board to CCS.

In our board we have 3 processor ,out of which 1 is configured as Centralized Processor (Called CP henceforth) and 2 Distributing Processors (Called DP henceforth). we need to send data from DP to CP through hyperlink .

I run the memoryMapped hyperlink example by commenting #define hyplnk_EXAMPLE_LOOPBACK in ti/drv/hyplnk/example/common/hyplnkLLDCfg.h.

Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
  Raw    = 0x4e902101
Status register contents:
  Raw        = 0x00003004
Link status register contents:
  Raw       = 0x00000000
Control register contents:
  Raw             = 0x00000000
Control register contents:
  Raw        = 0x00000000
============== end registers before initialization ===========

Hyperlink Serdes Common Init Complete
Invalid Serdes Lane Enable Init 4

 


Q1. only commenting #define hyplnk_EXAMPLE_LOOPBACK is enough to run the code between 2 boards[In our case 2 66AK2H14 processor]?

Regards,

Mahima shanbag

  • 0
    TI__Guru 65405 points
    The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Guru* 95265 points
    Hi,

    If you want to test board to board, the only change needed is commenting out #define hyplnk_EXAMPLE_LOOPBACK. I don't understand why you have "Invalid Serdes Lane Enable Init 4". Do you have this error in loopback mode? You may need to step into CSL_SerdesLaneEnable() to understand?

    Regards, Eric
  • 0 in reply to lding
    Expert 1585 points

    Hi Eric,

    1.

    I replaced  CSL_SERDES_LANE_ENABLE_LANE_INIT with CSL_SERDES_LANE_ENABLE_LANE_INIT_NO_WAIT as it was getting hang in the While loop , so I got Invalid Serdes Lane Enable Init 4 .

    When #define hyplnk_EXAMPLE_LOOPBACK is commented CCS was getting hang in the while loop of CSL_SerdesWaitForSigDet() function.Same issue is there in EVM also.

    2.

    In LOOPBACK mode Invalid Serdes Lane Enable Init 4 error is not there, application is running successfully.

    3.

    I just commented CSL_SerdesWaitForSigDet() function and flashed the same  to both 66ak2h14 processor , but it got hang with below log.

    Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09

    About to do system setup (PLL, PSC, and DDR)

    Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95

    system setup worked

    About to set up HyperLink Peripheral

    ============================Hyperlink Testing Port 0

    ========================================== begin registers before initialization ===========

    Revision register contents:

     Raw    = 0x4e902101

    Status register contents:

     Raw        = 0x00003004

    Link status register contents:

     Raw       = 0x00000000

    Control register contents:

     Raw             = 0x00000000

    Control register contents:

     Raw        = 0x00000000

    ============== end registers before initialization ===========

    Hyperlink Serdes Common Init Complete

    Hyperlink Serdes Lane 0 Init Complete

    Hyperlink Serdes Lane 1 Init Complete

    Hyperlink Serdes Lane 2 Init Complete

    Hyperlink Serdes Lane 3 Init Complete

    ============== begin registers after initialization ===========

    Status register contents:

     Raw        = 0x04402005

    Link status register contents:

     Raw       = 0xccf00cf0

    Control register contents:

     Raw             = 0x00006204

    ============== end registers after initialization ===========

    Waiting 5 seconds to check link stability

    Analyzing the connection for each lane

    Precursors 1

    Postcursors: 19

    Link seems stable

    About to try to read remote registers..


    I debugged step by step and go to know It was hanging at hyplnkExampleCheckOneStat (hyplnk_LOCATION_REMOTE, "after stability wait", 0);

    What may be the issue with remote register read?

    3.
    In LOOPBACK mode if I run the code for second time without reset , then also it was getting hang at


    Version #: 0x02010007; string HYPLNK LLD Revision: 02.01.00.07:May 25 2018:11:00:09
    About to do system setup (PLL, PSC, and DDR)
    Constructed SERDES configs: PLL=0x00000228; RX=0x0046c495; TX=0x000ccf95
    system setup worked
    About to set up HyperLink Peripheral
    ============================Hyperlink Testing Port 0
    ========================================== begin registers before initialization ===========
    Revision register contents:
      Raw    = 0x4e902101
    Status register contents:
      Raw        = 0x00003004
    Link status register contents:
      Raw       = 0x00000000
    Control register contents:
      Raw             = 0x00000000
    Control register contents:
      Raw        = 0x00000000
    ============== end registers before initialization ===========

    HIII
    Hyperlink Serdes Common Init Complete
    Hyperlink Serdes Lane 0 Init Complete
    Hyperlink Serdes Lane 1 Init Complete
    Hyperlink Serdes Lane 2 Init Complete
    Hyperlink Serdes Lane 3 Init Complete
    ============== begin registers after initialization ===========
    Status register contents:
      Raw        = 0x04402005
    Link status register contents:
      Raw       = 0xfdf0bdf0
    Control register contents:
      Raw             = 0x00006206
    ============== end registers after initialization ===========
    Waiting 5 seconds to check link stability
    Analyzing the connection for each lane
    Precursors 1
    Postcursors: 19
    Link seems stable
    About to try to read remote registers

    Why It is getting hang at this position?

    4.

    In Hyperlink some of the Tx/Rx P&N signals are swapped for ease of routing.. I think this wont create any software changes as per this link 

    Regards,

    Mahima Shanbag

  • 0 in reply to mahima shanbag
    Expert 1585 points
    Hi Eric,
    Waiting for your reply...

    Regards,
    Mahima Shanbag
  • 0 in reply to mahima shanbag
    TI__Guru* 95265 points
    Hi,

    For 1: "CSL_SERDES_LANE_ENABLE_LANE_INIT with CSL_SERDES_LANE_ENABLE_LANE_INIT_NO_WAIT"=========> please don't change this, you need to wait for the lane initialization finish

    When #define hyplnk_EXAMPLE_LOOPBACK is commented CCS was getting hang in the while loop of CSL_SerdesWaitForSigDet() function.Same issue is there in EVM also.=============> you need both sides running, otherwise it will not detect the Rx signal

    For 2: it is expected

    For 3: CSL_SerdesWaitForSigDet() ======> you should not comment this function out, this is to detect the signal from the remote side

    For 3: In LOOPBACK mode if I run the code for second time without reset =====> the code is designed to run one time, you need to reset or power cycle the board for each run

    For 4: no software change is needed.

    Regards, Eric