Tool/software: TI C/C++ Compiler
Dear TI Support Team,
I am using the C66xx linker version v8.2.3.
I found an issue around the automatic generated $fill sections.
I am working with OpenMP and need some non cachable memory inside of MSMCSRAM, for example:
MEMORY { L2SRAM (RWX) : org = 0x0080.0000, len = 0x0008.0000 // 512 kByte MSMCSRAM (RWX) : org = 0x0c02.0000, len = 0x000e.0000 // 896 kByte OMP_MSMC_NC_PHY (RW) : org = 0x0c00.0000, len = 0x0002.0000 // 128 kByte OMP_MSMC_NC_VIRT (RWX) : org = 0xa000.0000, len = 0x0002.0000 // 128 kByte DDR3 (RWX) : org = 0x8000.0000, len = 0x1f80.0000 // 248 MByte DDR3_LOCAL_PHY (RW) : org = 0x9f80.0000, len = 0x0080.0000 // 8 MByte DDR3_LOCAL_VIRT (RW) : org = 0xb000.0000, len = 0x0040.0000 // 4 MByte }
The OpenMP secific sections are something like that:
SECTIONS { .tomp_svNcMem: load= OMP_MSMC_NC_PHY, run= OMP_MSMC_NC_VIRT, fill = 0x0 .tomp_gvMem: load= L2SRAM, fill = 0x0 .tomp_svMemSlow: load= DDR3 }
Critical is the section .tomp_svNcMem, which is using different load and run addresses. The linker generates a $fill section located before the .tomp_svNcMem section, however the load address will be equal as the run address. At boot time the run address will be not available for the RBL, so that the RBL will write the $fill section to DDR3 and owerride other sections.
I have found a workaround, where I am using "--exclude=$fill*" parameter for the Hex6x tool.
Around that issue I have some questions:
- Please, would you confirm that here is a bug in the linker v8.2.3.
- What is the reason of the $fill sections?
Thanks and kind regards
Sven