Centaurus - Pin swap on DDR3 bus

Magnus,

Within a particular data byte it is OK to send a particular data bit to any of the DDR data bits since as long as the DSP reads back from the same bit it writes to then it will not even know that there has been a switching of the data bits.  You can only do this 'swizzling' within data bytes since there are other signals which are passed per byte, such as DQS, so the timing relationship between each DQS signal and its associated data byte must be maintained.  Note, you cannot do the same 'trick' with the address bits since specific 'commands' are sent across the address lines during DDR configuration, but there are no commands sent across the data lines so as long as the DSP reads back exactly what it writes, then the actual ordering does not matter.

Byte swapping is also OK.  The EMIF data bytes do not have to go to the "same" data bytes on the DDR memory devices, but the entire byte (data bits, data mask and DQS) must go to the same byte on the DDR device.  In other words, it is okay for byte1 of the DDR device to be connected to our device's byte0, but *all* of byte0 needs to go to byte1 of the memory device. Keep the entire bytes together and there will be no issue.

Regards,
Marc

Magnus,

Additional input from designer team:

I think swapping is definitely OK byte wise as long as all the DQ lines in that byte and corresponding DQS/DQSn and DQM control signals are all grouped … For example DQ[7:0],DQS0/DQSN0,DQM0 can be connected to DQS[15:8],DQS1/DQSN1,DQM1 of a memory device.

In general for DDR3, swapping the data lines within a byte may not be advisable as DDR3 device uses specific DQ lines during leveling process. However in Centaurus case, as the customers are recommended to use SW leveling, this restriction may not hold good though.

There is a lot of confusion here regarding the swapping of address lines. According to the JEDEC standard for DDR3 devices, there is built in support for what is called "two rank" address mirroring. In this case some of the address pins are swappable to allow for easier routing of signals for mirrored devices.

Does TI support this feature? If not then it is clear that signal will be crossed for the mirrored devices.

Comment?

BR

Michael Stamler

Viet,

According to the JEDEC DDR3 specification "Either one or all data bits ("prime DQ bit(s)") provide the leveling feedback". It is not defined which single DQ bit to be used as prime DQ bit by the DDR3 silicon. Various vendors could use different (or all) bits.

For that reason swapping of DQ bits within a given byte must be allowed, given that the controller is implemented according to DDR3 specification.

Is that the case ?

Michael,

Swapping A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 when mirroring rank 2 on UDIMM's makes sense with respect to PCB layout, but I haven't found any further details on what TI mean with the term "mirror" stated in the datasheet (other than simply placing a DDR3 device on the bottom). It has though been clearly stated that memory modules are not supported!

My assumption is that mirroring is not really supported by the memory controller, thereby leading to a more complex PCB layout of DDR3 devices mounted back to back.

Best regards,

Michael

Hi Michael,

This is from our DDR expert:

We do not support  fully hardware controlled auto leveling(also referred as HW leveling) for DDR IOs on DM814x. Customers should use the SW leveling approach instead.

BR,

Viet