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Detecting watchdog reset

Lee Nipper
Prodigy 60 points

In the Sitara manual, the PRM_RSTST register is documented as:

PRM_RSTST Register (offset = A8h) [reset = 1h]
PRM_RSTST is shown in Figure 2-183 and described in Table 2-197.
This register logs the global reset sources...

In particular, bit 3 as:

3 MPU_WDT_RST R/W 0h MPU Watchdog timer reset event. This is a source of global WARM
reset. [warm reset insensitive]
0 = 0x0 : No MPU watchdog reset.
1 = 0x1 : MPU wachtdog reset has occurred.

With our Sitara processors,  this register reads back as 0x00000009 all the time, where bit 3 indicates that a watchdog reset has occurred.

I'm looking for a way to detect on bootup whether a watchdog reset occurred previously.  The PRM_RSTST register seemed to be the best way to detect the reset source, but it is not reporting the value I would expect, since Bit 3 is ALWAYS ON.   Is there a way to make this work correctly ?

  • 0
    Prodigy 60 points

    An update...

    I've discovered that if the PRM_RSTST register is cleared on each boot (by writing the read value from the register),
    that when a watchdog reset actually _does_ occur, the register does report Bit 3 ON, and all other bits are clear.

    Problem solved.

  • 0 in reply to Lee Nipper
    Prodigy 20 points

    Hello,

    I'm running into this issue as well, where it's returning 0x9 all the time.  When exactly do you clear the PRM_RSTST register?

    Thanks

  • 0 in reply to Edison David
    Prodigy 60 points

    In evm.c, early in function board_init, just before the comment about UART softreset.
    I added these lines:

    #ifndef CONFIG_TI814X_MIN_CONFIG
       gd->bd->bi_reset_info = _raw_readl(PRM_DEVICE_RSTTST);
       _raw_writel(gd->bd->bi_reset_info, PRM_DEVICE_RSTTST);
    #endif

    I also added the bi_reset_info to struct bd_info in arch/arm/include/asm/u-boot.h for a place to save off the RSTTST bits before clearing them.
    And I added the lines below to arch/arm/include/asm/arch-ti81xx/cpu.h for the RSTTST register.

    #define PRM_DEVICE_RSTTST              (PRCM_BASE + 0x00A8)
    #define PRM_DEVICE_RSTTST_GLOBAL_COLD_RST       (BIT(0))    // Power-on (Cold) reset
    #define PRM_DEVICE_RSTTST_GLOBAL_WARM_SW_RST    (BIT(1))    // Warm software reset
    #define PRM_DEVICE_RSTTST_MPU_WDT_RST           (BIT(3))    // Watchdog reset

    And elsewhere I tested the bits.  One thing you probably will observe is that a cold powerup also has a 0x9 (cold + watchdog) in the register.
    So, when displaying any message, I ignore watchdog when the cold bit is set.  I also changed the reset_cpu to use warm reset instead of cold in both u-boot & kernel.
    With this arrangement, cold bit means cold reset,  warm bit means sw initiated reset, and watchdog bit really means watchdog reset.

    -Lee

  • 0 in reply to Lee Nipper
    Prodigy 20 points

    awesome, thanks! I was planning on ignoring the watchdog bit if the cold bit is set, so good to know you're already doing that.