How to set DM8148 SD_VENC to By-pass Mode?

Hi Mike,

In which section of the DM814x DataSheet or TRM the SD_VECN in bypass mode is stated as a possible option?

I have check DM814x TRM, section 12.9 Standard-Definition Video Encoder (SD-VENC) Module, and I can not locate bypass mode inside the supported modes/features.

Regards,

Pavel

Hi,

SD VENC does not have any bypass bit, i could not get any bypass bit in SD VENC specs..

Regards,

Brijesh Jadav

Hi,

The TVOUT Bi-pass mode I am referring to is described in "Table 3-47. Video Output (Analog, TV) Terminal Functions" of the DM8148 DataSheet.  I found the control bit in SD_DAC_CTRL Register in the TRM this morning (in the CONTROL_MODULE).  I don't see a way to set it via sysfs , so I will edit the kernel and configure it there.  Sorry for the trouble. 

Margarita,  thanks for the examples for videotestsrc, but I was more interested in something that specifically drove the /dev/video3 on the EVM (the s-video or composite output using the On-Chip video DACs).  Do you have anything for that, or is there program in the EzSDK that will exercise the SD outputs to support hardware validation?

Thanks for your quick responses.

-Mike

Hi,

Still having some trouble.  I am using devmem2 to modify the bit.  It seems to take, but then gets immediately cleared.  Any ideas?

-Mike

# set the bit....

/sys/devices/platform/vpss/display2 # devmem2 0x48140670 w 0x0188001DB          
/dev/mem opened.                                                                
Memory mapped at address 0x4004c000.                                            
Read at address  0x48140670 (0x4004c670): 0x018800DB                            
Write at address 0x48140670 (0x4004c670): 0x188001DB, readback 0x188001DB       

#check the bit is still set....

/sys/devices/platform/vpss/display2 # devmem2 0x48140670 w                      
/dev/mem opened.                                                                
Memory mapped at address 0x4023a000.                                            
Read at address  0x48140670 (0x4023a670): 0x018800DB  

Hi Mike,

It may not allow to changes those bits from the user space, you will need to change them in the Linux kernel space.

Regards,

Brijesh Jadav

Hi Brijesh,

It looks like that register is controlled via the M3 software via a vps_fvid2_control() call.

I don't see support for setting the BYPASS mode bit in the include/linux/vps_displayctrl.h header file.

Will the M3 leave it alone or am I out of luck without an update to the M3 firmware?

-Mike

Hi,

I was able to add some simple sysfs controls to enable/disable the color bar generation for SD VENC / DAC output, as well as enable/disable bypass mode and enable/disable the invert mode (by default, the output is inverted).

Using these controls allowed us to use our required external filters / amps instead of the internal ones.

I have attached the patch used, in case someone else runs across this issue in the future.

(Margarita, I was also able to generate test patterns to /dev/video3 using your examples as reference).

Thanks for your assistance.

-Mike

diff --git a/drivers/video/ti81xx/vpss/dctrl.c b/drivers/video/ti81xx/vpss/dctrl.c
index 7e8697b..82b88a1 100644
--- a/drivers/video/ti81xx/vpss/dctrl.c
+++ b/drivers/video/ti81xx/vpss/dctrl.c
@@ -2315,6 +2315,174 @@ static ssize_t blender_edid_show(struct dc_blender_info *binfo, char *buf)
return l;
}

+static ssize_t blender_bypass_store(struct dc_blender_info *binfo,
+ const char *buf,
+ size_t size)
+{
+ unsigned int val;
+ unsigned int tmp;
+ void __iomem *pbase;
+
+ if (binfo->idx != SDVENC) {
+ VPSSERR("Bypass only valid for SDVENC\n");
+ return -EINVAL;
+ }
+ sscanf(buf, "%u", &val);
+
+ pbase = ioremap(0x48140670, 4);
+ if (pbase) {
+ tmp = __raw_readl((u32)pbase);
+ if (val)
+ tmp |= 0x100;
+ else
+ tmp &= ~(0x100);
+ __raw_writel(tmp, (u32)pbase);
+ tmp = __raw_readl((u32)pbase);
+ iounmap(pbase);
+ } else {
+ VPSSERR("Could not map SD_DAC register\n");
+ return -EINVAL;
+ }
+
+ return size;
+}
+
+static ssize_t blender_bypass_show(struct dc_blender_info *binfo, char *buf)
+{
+ int r;
+ unsigned int tmp;
+ void __iomem *pbase;
+
+ if (binfo->idx == SDVENC) {
+ pbase = ioremap(0x48140670, 4);
+ if (pbase) {
+ tmp = __raw_readl((u32)pbase);
+ r = snprintf(buf, PAGE_SIZE, "%d\n", (tmp & 0x100) ? 1 : 0);
+ printk( KERN_INFO "SD_DAC_CTRL is %08X\n", tmp);
+ iounmap(pbase);
+ } else {
+ VPSSERR("Could not map SD_DAC register\n");
+ return -EINVAL;
+ }
+ } else {
+ VPSSERR("Bypass only valid for SDVENC\n");
+ return -EINVAL;
+ }
+ return r;
+}
+
+static ssize_t blender_invert_store(struct dc_blender_info *binfo,
+ const char *buf,
+ size_t size)
+{
+ unsigned int val;
+ unsigned int tmp;
+ void __iomem *pbase;
+
+ if (binfo->idx != SDVENC) {
+ VPSSERR("Invert only valid for SDVENC\n");
+ return -EINVAL;
+ }
+ sscanf(buf, "%u", &val);
+
+ pbase = ioremap(0x48140670, 4);
+ if (pbase) {
+ tmp = __raw_readl((u32)pbase);
+ if (val)
+ tmp |= 0x40;
+ else
+ tmp &= ~(0x40);
+ __raw_writel(tmp, (u32)pbase);
+ tmp = __raw_readl((u32)pbase);
+ iounmap(pbase);
+ } else {
+ VPSSERR("Could not map SD_DAC register\n");
+ return -EINVAL;
+ }
+
+ return size;
+}
+
+static ssize_t blender_invert_show(struct dc_blender_info *binfo, char *buf)
+{
+ int r;
+ unsigned int tmp;
+ void __iomem *pbase;
+
+ if (binfo->idx == SDVENC) {
+ pbase = ioremap(0x48140670, 4);
+ if (pbase) {
+ tmp = __raw_readl((u32)pbase);
+ r = snprintf(buf, PAGE_SIZE, "%d\n", (tmp & 0x40) ? 1 : 0);
+ printk( KERN_INFO "SD_DAC_CTRL is %08X\n", tmp);
+ iounmap(pbase);
+ } else {
+ VPSSERR("Could not map SD_DAC register\n");
+ return -EINVAL;
+ }
+ } else {
+ VPSSERR("Invert only valid for SDVENC\n");
+ return -EINVAL;
+ }
+ return r;
+}
+
+static ssize_t blender_colorbar_store(struct dc_blender_info *binfo,
+ const char *buf,
+ size_t size)
+{
+ unsigned int val;
+ unsigned int tmp;
+ void __iomem *pbase;
+
+ if (binfo->idx != SDVENC) {
+ VPSSERR("Colorbar only valid for SDVENC\n");
+ return -EINVAL;
+ }
+ sscanf(buf, "%u", &val);
+
+ pbase = ioremap(0x48105E04, 4);
+ if (pbase) {
+ tmp = __raw_readl((u32)pbase);
+ if (val)
+ tmp |= 0x10;
+ else
+ tmp &= ~(0x10);
+ __raw_writel(tmp, (u32)pbase);
+ tmp = __raw_readl((u32)pbase);
+ iounmap(pbase);
+ } else {
+ VPSSERR("Could not map VPSS SDVENC CONTRL register\n");
+ return -EINVAL;
+ }
+
+ return size;
+}
+
+static ssize_t blender_colorbar_show(struct dc_blender_info *binfo, char *buf)
+{
+ int r;
+ unsigned int tmp;
+ void __iomem *pbase;
+
+ if (binfo->idx == SDVENC) {
+ pbase = ioremap(0x48105E04, 4);
+ if (pbase) {
+ tmp = __raw_readl((u32)pbase);
+ r = snprintf(buf, PAGE_SIZE, "%d\n", (tmp & 0x10) ? 1 : 0);
+ printk( KERN_INFO "VPSS SDVENC CONTRL is %08X\n", tmp);
+ iounmap(pbase);
+ } else {
+ VPSSERR("Could not map SDVENC register\n");
+ return -EINVAL;
+ }
+ } else {
+ VPSSERR("Colorbar only valid for SDVENC\n");
+ return -EINVAL;
+ }
+ return r;
+}
+
struct blender_attribute {
struct attribute attr;
ssize_t (*show)(struct dc_blender_info *, char *);
@@ -2344,6 +2512,12 @@ static BLENDER_ATTR(source, S_IRUGO | S_IWUSR,
/* currently EDID read only */
static BLENDER_ATTR(edid, S_IRUGO,
blender_edid_show, NULL);
+static BLENDER_ATTR(bypass, S_IRUGO | S_IWUSR,
+ blender_bypass_show, blender_bypass_store);
+static BLENDER_ATTR(colorbar, S_IRUGO | S_IWUSR,
+ blender_colorbar_show, blender_colorbar_store);
+static BLENDER_ATTR(invert, S_IRUGO | S_IWUSR,
+ blender_invert_show, blender_invert_store);

static struct attribute *blender_sysfs_attrs[] = {
&blender_attr_mode.attr,
@@ -2355,6 +2529,9 @@ static struct attribute *blender_sysfs_attrs[] = {
&blender_attr_name.attr,
&blender_attr_edid.attr,
&blender_attr_source.attr,
+ &blender_attr_bypass.attr,
+ &blender_attr_colorbar.attr,
+ &blender_attr_invert.attr,
NULL
};