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using single DDR

ranchu
Guru 20755 points

Hello,

I've patched u-boot to use single DRAM bank it seems to be all OK.

These are the configuration I'm using:

#define USE_EMIF0              1
#define USE_EMIF1            0

The only issue I had was wrong print (512M uinstead of 256M).

When I tried to change as following:

from old:

#define CONFIG_NR_DRAM_BANKS 2

to new:

#define CONFIG_NR_DRAM_BANKS 1

The 1st u-boot get stack.

Is there any idea what I can do ?

Thank you,

Ran

  • 0
    TI__Guru**** 170625 points

    Hi Ran,

    I have tested this on the DM814x TI EVM with the below u-boot:
    http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    I made the below modifications on this u-boot code base:

    /include/configs/ti8148_evm.h

    /**
    * Physical Memory Map
    */
    //#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
    #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
    #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
    //#define PHYS_DRAM_1_SIZE 0x20000000 /* 512 MB */
    #define PHYS_DRAM_1_SIZE 0x10000000 /* 256 MB */
    //#define PHYS_DRAM_2 0xA0000000 /* DRAM Bank #2 */
    //#define PHYS_DRAM_2_SIZE 0x20000000 /* 512 MB */

    /board/ti/ti8148/evm.c

    /*
    * sets uboots idea of sdram size
    */
    int dram_init(void)
    {
    /* Fill up board info */
    gd->bd->bi_dram[0].start = PHYS_DRAM_1;
    gd->bd->bi_dram[0].size = PHYS_DRAM_1_SIZE;

    //gd->bd->bi_dram[1].start = PHYS_DRAM_2;
    //gd->bd->bi_dram[1].size = PHYS_DRAM_2_SIZE;

    return 0;
    }

    Then both 1st stage and 2nd stage u-boot does not stuck and reports 256MB RAM:

    U-Boot 2010.06 (Jun 01 2015 - 16:19:14)

    TI8148-GP rev 2.1

    ARM clk: 600MHz
    DDR clk: 400MHz

    DRAM: 256 MiB
    DCACHE: Off

    TI-MIN#go 0x81000000
    ## Starting application at 0x81000000 ...


    U-Boot 2010.06 (Jun 01 2015 - 16:12:38)

    TI8148-GP rev 2.1

    ARM clk: 600MHz
    DDR clk: 400MHz

    I2C: ready
    DRAM: 256 MiB
    DCACHE: On

    BR
    Pavel

  • 0 in reply to Pavel Botev
    Guru 20755 points
    Hi Pavel,

    Thank you very much!

    I missed at first try the change in dram_init(), that's why it didn't work in the first run.
    I think it would be better to put it into a define, so that it will all be under single flag:
    CONFIG_NR_DRAM_BANKS (2 - for both banks, 1 - single bank).
    That's what I did in code for the dram_init:

    #if CONFIG_NR_DRAM_BANKS == 2
    gd->bd->bi_dram[1].start = PHYS_DRAM_2;
    gd->bd->bi_dram[1].size = PHYS_DRAM_2_SIZE;
    #endif

    Thank you for assistance,
    Ran