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DM8148 custom board RGMI lines to FPGA

kiran patil96658
Intellectual 550 points

Hi all,


We have a DM8148 custom board, where RGMII lines are connected to FPGA.In uboot or kernel, they look for a phy and then transmits the packets.

Our requirement is not  to configure phy but to transmit packets, so what are changes need to be done in uboot and kenel

We are working on DVR_RDK_04_01_00_02. We struck in the board bring up, any help would be appreciated.

Regards,

Kiran S Patil

  • 0
    TI__Guru**** 170625 points
    Hi Kiran,

    In DM814x TI EVM, RGMII lines and MDIO lines are connected to PHY. MDIO interface (clock & data) is connected out to control the PHY configuration and status monitoring. From what I understand you need to remove the MDIO functionality.

    The MDIO lines are at PAD233 and PAD234 and configured in u-boot/board/ti/ti8148/evm.c

    static void cpsw_pad_config()
    {
    volatile u32 val = 0;

    /*configure pin mux for rmii_refclk,mdio_clk,mdio_d */
    val = PAD232_CNTRL;
    PAD232_CNTRL = (volatile unsigned int) (BIT(18) | BIT(0));
    val = PAD233_CNTRL;
    PAD233_CNTRL = (volatile unsigned int) (BIT(19) | BIT(17) | BIT(0));
    val = PAD234_CNTRL;
    .....
    }

    If you are planning to not using the MDIO, you can set this pins as GP1[10] and GP1[11].

    The MDIO functionality is implemented in the Ethernet driver:
    u-boot/drivers/net/cpsw.c

    int cpsw_register(struct cpsw_platform_data *data)
    {
    ....
    cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);

    return 1;
    }

    The MDIO functions are: cpsw_mdio_init, wait_for_user_access, wait_for_idle, cpsw_mdio_read, cpsw_mdio_write.

    See also if the below wiki page will be in help:
    processors.wiki.ti.com/.../TI81xx_PSP_Porting_Guide

    BR
    Pavel