I AM USING DM814x , by using a boot loader i am copying my program image to RAM from Flash , Image copying stucks when Copying Section of program to DUCATI BASE ADDRESS .

Ammar

I AM USING DM814x , by using a boot loader i am copying my program image to RAM from Flash , Image copying stucks when Copying Section of program to DUCATI BASE ADDRESS . i am not understanding why ? and how to solve this issue . program works fine while debug mode.

Ammar Zafar

over 9 years ago

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Hi Ammar,

Do you work from the u-boot prompt (TI8148_EVM#)? What is this program image that you copy? At which address in RAM exactly you copy to?

Can you provide console log for the failing case and for the successful (debug mode) case?

Regards,
Pavel

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thanks Pavel for reply,

No its a SBl package , which has spi.out for flashing images.

its flashesh the program image to SPI FLASH , then boot loader provided in SBl configure the settings and start copying image sections to the specified address ,

I am facing problem when my section address is 0x0 for M3 in program it actually sums it up to Ducatii base address which is 0x55020000

it stucks there , and wait for edma transfer .

0 Pavel Botev over 9 years ago in reply to Ammar

TI__Guru**** 170625 points

Ammar,

From which initiator you are trying to access the Media Controller (Cortex-A8 MPU, PCIe, DAP/JTAG, EDMA)?

Can you access Media Controller registers like CACHE_CONFIG/0x55000004, CACHE_INT/0x55000008? Note that Media Controller (Cortex-M3 MPU, Ducati) base address is 0x55000000. And there is 64KByte RAM inside this Media Controller, which start address is 0x55020000.

Can you also provide me the values of the below registers? I need the values in the moment just before trying to access Media Controller.

CM_DEFAULT_DUCATI_CLKSTCTRL
CM_DEFAULT_DUCATI_CLKCTRL
RM_DEFAULT_RSTCTRL
RM_DEFAULT_RSTST
MEDIA_CONTROLLER_MEM_PWRDN

Regards,
Pavel

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thank You Pavel for Reply ,

The base address of Ducati is defined in the file provided in the package .
Accessing it using EDMA .

The program is working in debug mode.

The boot loader is able to turn on the HDMI and i can see The Colored lines on the screen.
Image copy is working fine with dsp and A8 programs . Program stucks when EDMA is accessing section Address at the below mentioned Ducati base.

if all the Sections have section greater than 0x80000000 there is no issue.

//Ducati - CLK CTRL
#define CM_DEFAULT_DUCATI_CLKSTCTRL (PRCM_BASE_ADDR + 0x0518)
#define CM_DEFAULT_DUCATI_CLKCTRL (PRCM_BASE_ADDR + 0x0574)

//Ducati - Warm Reset Clk register
#define DUCATI_BASE_ADDR (0x55020000)
#define RM_DEFAULT_RSTCTRL (PRCM_BASE_ADDR + 0x0B10)
#define RM_DEFAULT_RSTST (PRCM_BASE_ADDR + 0x0B14)

was not able to find MEDIA_CONTROLLER_MEM_PWRDN in the file .

Regards,
Ammar Zafar

0 Pavel Botev over 9 years ago in reply to Ammar

TI__Guru**** 170625 points

Ammar said:
The program is working in debug mode.

Can you identify the differences between working (debug) mode and non-working mode?

Ammar said:
Program stucks when EDMA is accessing section Address at the below mentioned Ducati base.

Ammar said:
#define DUCATI_BASE_ADDR (0x55020000)

This is Ducati RAM memory base address. Can you try to access it from Cortex-A8 (or JTAG) (not EDMA), will this work fine?

Ammar said:
if all the Sections have section greater than 0x80000000 there is no issue.

I do not get this. Can you provide more details?

Ammar said:
//Ducati - CLK CTRL
#define CM_DEFAULT_DUCATI_CLKSTCTRL (PRCM_BASE_ADDR + 0x0518)
#define CM_DEFAULT_DUCATI_CLKCTRL (PRCM_BASE_ADDR + 0x0574)

Ammar said:
//Ducati - Warm Reset Clk register

Ammar said:
#define RM_DEFAULT_RSTCTRL (PRCM_BASE_ADDR + 0x0B10)
#define RM_DEFAULT_RSTST (PRCM_BASE_ADDR + 0x0B14)

I am aware of these registers offsets. What I need to know is the value in this registers.

Ammar said:
was not able to find MEDIA_CONTROLLER_MEM_PWRDN in the file .

This should not prevent you from getting the value from this register. The full address is 0x4814065C, the offset is 0x65C.

You can try to add it, should be something like:

#define MEDIA_CONTROLLER_MEM_PWRDN (CONTROL_MODULE + 0x065C)

Regards,
Pavel

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thank you pavel ,

CM_DEFAULT_DUCATI_CLKSTCTRL=0x702
CM_DEFAULT_DUCATI_CLKCTRL=0x2
RM_DEFAULT_RSTCTRL=0xE3
RM_DEFAULT_RSTST=0x1C
MEDIA_CONTROLLER_MEM_PWRDN=0;

These are the values of the registers after boot is done , before the its copies Application Image from Spi flash and load section into Ram.

BR
Ammar Zafar

0 Ammar over 9 years ago in reply to Ammar

Expert 2230 points

Pavel ,

This is Ducati RAM memory base address. Can you try to access it from Cortex-A8 (or JTAG) (not EDMA), will this work fine?
Yes my program works with JTAG .

For now instead copying the bootloader in SPI Flash , i am running the program sequence in Cortex A8. which configure the Board and then copy application image from specified address.

My program is stucks when i am trying to store a value present in Ducati Base Ram address to a variable.

BR
Ammar Zafar

0 Pavel Botev over 9 years ago in reply to Ammar

TI__Guru**** 170625 points

Ammar,

Than the problem might be in the EDMA (not in Ducati RAM). Are you sure EDMA is configured correct? Can you test with EDMA transfer to the DDR3 memory?

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thank You pavel For helping me ,
EDMA Is copying program fine , have copied DSP and A8 with it .

i am able to move forward with program by adding before reading from Ducati section

{
(*(volatile unsigned int*)RM_DEFAULT_RSTCTRL) |= (0x1<<3);
/* clear the status bit only if it is set*/
if( RD_MEM_32(RM_DEFAULT_RSTST) & 0x8)
{
(*(volatile unsigned int*)RM_DEFAULT_RSTST) = 0x8;
m31++;
}
}
still the boot is complete and my programm sections are at place but its not working still ,
I am attaching my memory map , it seems to me the sections .

two of the section not in External Ram 0x80000000

are placed at a location = Ducati Base Ram address+ address of section.

I can attached the memory map generated , if you want ?
connecting in ccs to the M3 core after color lines are displayed its say 0x6800480C no symbol defined

and loading anything gives the status ducati core rest = 0x00000008

My Entry point ix 0x9

0 Pavel Botev over 9 years ago in reply to Pavel Botev

TI__Guru**** 170625 points

Ammar,

In DM814x EVM GEL file we have these kind of code:

#define DUCATI_BASE_ADDR 0x55020000

#define DUCATI_MMU_CFG 0x55080000

GEL_MapAddStr( 0x55000000, 0, 0x01000000, "R|W|AS4", 0 ); // Ducati Slave Port

/*Write Ducate IRAM Boot Image */

WR_MEM_32(DUCATI_BASE_ADDR, 0x10000);

WR_MEM_32(DUCATI_BASE_ADDR+0x4, 0x9);

WR_MEM_32(DUCATI_BASE_ADDR+0x8, 0xE7FEE7FE);

WR_MEM_32(DUCATI_MMU_CFG+0x9A0, 0x55020000);

Do you have something similar on your side?

If you initialized your DM814x board with the standard GEL file, the L2 RAM memory is re-mapped to address range 0x00000000..0x0000FFFF.

0x00000000 is a virtual memory-mapped address that is supposed to be mapped to the Ducati L2 RAM at 0x55020000. The Ducati MMU performs this address translation and must be configured so that the first small page maps 0x00000000 to 0x55020000. You can quickly diagnose whether the AMMU mapping exists by opening a memory window in CCS, writing a word to 0x55020000 and see if the same data is can be viewed at 0x00000000.

This page maps VA=0x00000000 to PA=0x55020000. This is necessary for boot, since when you take the M3 out of reset it will execute from address 0x00000000 which you want to map to the local RAM.

logical 0x00000000 -> physical 0x55020000 - This is required because M3 on taken out of reset jumps to logical address 0x00000000 which is mapped to L2 start address and reset vector is placed at that address by sysbios.

Note that first 16KB (L2_BOOT) are reserved for reset vectors and are mapped to 0x00000000. Hence the L2 RAM section starts at 0x55024000. Can you try with that address?

BIOS based ducati applications currently dedicate the first 3k byte of RAM to reset vector, boot code, vector tables. Ram above is free to be used by the application.

Regards,
Pavel

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thank You so much Pavel , I am looking in to it and will let you know .

Yeah i can see that 0x55020000 data to be on 0x0 , but ducati core seem to be at address of 0x68xxxxxxx..

BR
Ammar

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

this is working memory map.

0 Ammar over 9 years ago in reply to Ammar

Expert 2230 points

This one is with bootloader.

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thank you Pavel , let me explain the Procedure again .

SBL do booting in SPI mode. It copies the RPRC images(application images of different cores) from non-XIP memory device, parses & loads the RPRC images of all cores into DDR.

Ammar

0 Pavel Botev over 9 years ago in reply to Ammar

TI__Guru**** 170625 points

Ammar said:
Yeah i can see that 0x55020000 data to be on 0x0 , but ducati core seem to be at address of 0x68xxxxxxx..

Is this 0x68xxxxxx a virtual or physical address? The physical address range of 0x60000000 to 0x7FFFFFFF is for DDR DMM TILER Window, I do not see how the ducati core will go to that address.

Regards,
Pavel

0 Pavel Botev over 9 years ago in reply to Ammar

TI__Guru**** 170625 points

Ammar said:
SBL do booting in SPI mode. It copies the RPRC images(application images of different cores) from non-XIP memory device, parses & loads the RPRC images of all cores into DDR.

In this procedure, I do not see how the Ducati L2 RAM is involved? You copy from SPI flash to DDR3 memory, why Ducati L2 RAM involved and how?

BR
Pavel

0 Ammar over 9 years ago in reply to Pavel Botev

Expert 2230 points

Thank you Pavel for help , The issue has been resolved .

There was the ducati base address issue , the adjustment in the code solved it .

Thank You again for all your help . :)

BR
Ammar

0 Pavel Botev over 9 years ago in reply to Ammar

TI__Guru**** 170625 points

Ammar,

Glad to know you solve it. Can you close this thread with click on the "Verify Answer" button?

Can you also share info about the ducati base address adjustment in the code that solve it?

Regards,
Pavel

Processors

Processors forum

I AM USING DM814x , by using a boot loader i am copying my program image to RAM from Flash , Image copying stucks when Copying Section of program to DUCATI BASE ADDRESS .