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DM385/DM388 support

Other Parts Discussed in Thread: DM388, DM385

Dear Sirs,

1.We would like to get the IPNC SDK from 3rd party,Do we need to have IPNC license from TI first?

2.We would like to implement the "deep sleep mode" function on dm385/dm388,Do you have any software/hardware documents for us reference?

thank's

Best Regards,

Byron

  • Hi sir,

    1.We would like to get the IPNC SDK from 3rd party,Do we need to have IPNC license from TI first?

    2.We would like to implement the "deep sleep mode" function on dm385/dm388,Do you have any software/hardware documents for us reference? thank's.

    Best Regards,

    Byron

  • Hi Byron,

    DeepSleep mode is an extra power saving state in addition to what is being saved in StandBy mode. You will need a DM813x/DM38x TI EVM board or DM813x/DM38x custom board, where OSC_WAKE pin is attached to SW button, to be able to test DeepSleep support.

    Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal oscillator to further eliminate all active power. The device core voltages can be reduced for optimal power savings.

    See the below pointers for more info:
    e2e.ti.com/.../339366
    e2e.ti.com/.../637519

    Regards,
    Pavel
  • Byron Tien said:
    1.We would like to get the IPNC SDK from 3rd party,Do we need to have IPNC license from TI first?

    I will notify the IPNC RDK team to comment here.

    BR
    Pavel

  • Dear Pavel,

    Thank's for your response.
    It seem to have support OSC_WAKE  pin on DM385/DM388 to control DeepSleep mode.Is it right?
    How about the software side?How do we control this pin for this mode?
    Thank's.

    Best Regards,
    Byron

  • Byron Tien said:
    It seem to have support OSC_WAKE  pin on DM385/DM388 to control DeepSleep mode.Is it right?

    Right, the physical pin is U28/DEVOSC_WAKE controlled by PINCNTL7/0x48140818

    Byron Tien said:
    How about the software side?How do we control this pin for this mode?

    Refer to the wiki page below:

    See also:

    Regards,
    Pavel

  • Note also that there is possible issue with the current DeepSleep implementation (random hang). During the hang condition, the SW is in a loop waiting on the DSCOMPLETE bit to be set to 1 in the deep sleep status register. See the below file:

    linux-ipnc-rdk-dm81xx/arch/arm/mach-omap2/sleep814x.S

    #define DEEPSLEEP_CONTROL 0x324
    #define DEEPSLEEP_STATUS 0x328

    ds_completion_loop:
    ldr r8, [r3, #DEEPSLEEP_STATUS]
    and r8, r8, #0x1 @poll for DSCOMPLETE
    cmp r8, #0x1 @ == 1 if DSCOUNT equals timer
    bne ds_completion_loop

    The root cause about this possible hang is the reason that Sleep Enable input signal is coming from a clock domain which is different from the OSC clock. These clock domains are asynchronous. Hang caused by the SW implementation which waits for the DSCOMPLETE indefinitely on wakeup.

    SW workaround:
    Instead of waiting indefinitely on the DSCOMPLETE event, ensure the wait time is set to DSCOUNT delay + additional delay (margin). This will ensure the system recovers even if it fails to go to deep sleep.


    Regards,
    Pavel
  • Hi Pavel,

    Any update on above post ?thank's.

    Best Regards,

    Byron

  • Hi Sir,

    Thank's. for your description.So if we would like to control deep sleep mode.

    1.Enter deep sleep mode

    >>triggers suspend through sysfs entry - /sys/power/state.

     means that input the parameter into /sys/power/state by s/w?What the parameters we need to input?

    2.Wake up

    >>OSC_WAKE switch pressed - User enable the OSC clock by pressing OSC_WAKE.

     means that pin has to be wired to a button . When you need to wake it up, push that button.??

    BTW,how about the IPNC license issue?

    thank's.

    Best Regards,

    Byron

  • Byron Tien said:
    Any update on above post ?

    What kind of update on which post exactly?

  • Dear Sir,

    Sorry,My question

    if we would like to control deep sleep mode.

    1.Enter deep sleep mode

    >>triggers suspend through sysfs entry - /sys/power/state.

    means that input the parameter into /sys/power/state by s/w?What the parameters we need to input?

    2.Wake up

    >>OSC_WAKE switch pressed - User enable the OSC clock by pressing OSC_WAKE.

    means that pin has to be wired to a button . When you need to wake it up, push that button.??

    BTW,how about the IPNC license issue?If we would like to get the IPNC rdk code from 3rd party,do we need to have IPNC license from TI first?

    thank's.


    Best Regards,
    Byron
  • Byron,

    Byron Tien said:
    if we would like to control deep sleep mode.

    1.Enter deep sleep mode

    >>triggers suspend through sysfs entry - /sys/power/state.

    means that input the parameter into /sys/power/state by s/w?What the parameters we need to input?

    You need to input "mem"

    # echo -n "mem" > /sys/power/state

    But before to pass "mem" parameter to /sys/power/state, you need to change from the StandBy mode (default mode) to DeepSleep mode, using the
    enable_deep_sleep flag.

    The steps are:
    1.Mount debugfs
    2. set to 1 enable_deep_sleep flag
    3. pass "mem" to /sys/power/state

    More info you can find in the below wiki:



    Byron Tien said:
    2.Wake up

    >>OSC_WAKE switch pressed - User enable the OSC clock by pressing OSC_WAKE.

    means that pin has to be wired to a button . When you need to wake it up, push that button.??

    Correct

    Byron Tien said:
    BTW,how about the IPNC license issue?If we would like to get the IPNC rdk code from 3rd party,do we need to have IPNC license from TI first?


    I have never heard about IPNC license, but I am not IPNC expert. You can check this with your local TI FAE.

    Pavel

  • Byron Tien said:
    BTW,how about the IPNC license issue?If we would like to get the IPNC rdk code from 3rd party,do we need to have IPNC license from TI first?

    Even there is license requirement, this should be handled with TI FAE or sale representative. I do not see how license can be handle over public forum!

    Regards,
    Pavel

  • Dear Pavel,

    What's the status we can check if we change the deep sleep mode?

    Best Regards,
    Byron
  • Byron,

    You can monitor the DeepSleep related registers: DEEPSLEEP_CTRL and DEEPSLEEP_STATUS. Check the values there when executing StandBy and when executing DeepSleep, there should be difference.

    You can also track the linux kernel flow and check whether it enters into DeepSleep mode through the kernel messages, enable the pm debug.

    linux-ipnc-rdk-dm81xx/arch/arm/mach-omap2/cm-regbits-81xx.h
    linux-ipnc-rdk-dm81xx/arch/arm/mach-omap2/pm-debug.c
    linux-ipnc-rdk-dm81xx/arch/arm/mach-omap2/sleep814x.S
    linux-ipnc-rdk-dm81xx/arch/arm/mach-omap2/pm81xx.c

    Also when executing DeepSleep, the device oscillator (OSC0/DEVOSC) should be gated, no clock signal will go out of it. You can also check this.

    And during DeepSleep, active power consumption should be less that StandBy mode, around 0.8V, you can also check this.

    BR
    Pavel
  • Hi Pavel,

    Thank's for your reply.We still have some questions on this topic.Please help,thank's.

    1.

    You mean that  Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal oscillator to further eliminate all active power. The device core voltages can be reduced for optimal power savings.

    So if we enter this mode,Will those behaviors("the addition of gating the crystal oscillator to further eliminate" and "device core voltages can be reduced") be activated by system automatically without adjusting any hardware design?or we need to adjust our hardware design?

    2.

    Yesterday we got a DM385 IPNC EVM board.we found that the OSC_WAKE pin on EVM seem to tie with PullUp directly not  wire to a button.We are so confused.Why are they different? Is it  just the potential changed(high or low)? Do we need to adjust our hardware design?or we also tie it with PullUp?

    Do you have any hardware design with OSC_WAKE pin for our reference? 

    thank's a lot.

    Best Regards,

    Byron

  • Byron Tien said:

    You mean that  Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal oscillator to further eliminate all active power. The device core voltages can be reduced for optimal power savings.

    So if we enter this mode,Will those behaviors("the addition of gating the crystal oscillator to further eliminate" and "device core voltages can be reduced") be activated by system automatically without adjusting any hardware design?or we need to adjust our hardware design?

    If DeepSleep is enabled, suspend sequence will cut the Cortex-A8 ARM clock, else (in StandBy mode) Cortex-A8 ARM will remain active and will enter idle state.

    Then to be able to wake-up from DeepSleep, you will need to adjust your custom board to have button to enable the OSC clock.

    DeepSleep suspend/resume is handled by SW, you will only need to have button for the Wake-up.

    Byron Tien said:

    Yesterday we got a DM385 IPNC EVM board.we found that the OSC_WAKE pin on EVM seem to tie with PullUp directly not  wire to a button.We are so confused.Why are they different? Is it  just the potential changed(high or low)? Do we need to adjust our hardware design?or we also tie it with PullUp?

    Do you have any hardware design with OSC_WAKE pin for our reference? 

    Regarding DM385 IPNC EVM questions, you can ask your DM385 IPNC EVM supplier. Check for the latest version of the EVM.

    The DM814x TI EVM has OSC_WAKE button only in the latest version of the board (rev D). You can get the latest documents for DM814x TI EVM from the Mistral web site:

    HARDWARE -> Downloads for TMDXEVM8148 – Base Board -> Rev - D -> Schematics -> PDF Format

  • Hi Pavel,

    thank you.

    How about the power consumption?When we enter the deep sleep mode,how much power consumption per component??

    Best Regards,

    Byron

  • Byron,

    I have not tested this, I can not say. What I can find is that in DeepSleep mode, the Core Logic Voltage is 0.83V. See also if the below e2e threads will be in help:

    e2e.ti.com/.../446694
    e2e.ti.com/.../416392

    Regards,
    Pavel