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Netra: Query regarding "PAGESIZE" of SDRCR register

sweta bhatt
Expert 2345 points


Hi,

I have a query regarding PAGESIZE field of SDRAM configuration register for Netra (SDRAM Configuration Register (SDRCR)).

Bitwise description as per Tech ref manual is as below.

 We are designing our own hardware with different DDR3 chip than EVM.

Configurations of DDR3 chip: Row bits A0-A13, Column bits A0-A9, Page size 2 KB.

Thus, for page size of 2048, total 10 column address bits are required, but according to datasheet, if we set PAGESIZE=3H, then it will use 11 column address bits.

Note: IBANKPOS is set to 0, which indicates that only IBANK, EBANK and PAGESIZE will be used to identify row, column, bank and chip select.

Can someone confirm whether this will work or it will impact addressing scheme ?

Thanks in advance,

Sweta 

  • 0
    TI__Mastermind 25055 points

    Hello,

    The pagesize in the SDRCR is defined in terms of number of words, where a word is equal to DRAM data bus width. Therefore, a 2K pagesize would be 2K words.

    For 16-bit wide DRAM, with column bits A0-A9, the page size is 2KBytes or 1K words. Therefore, the pagesize in the SDRCR must be programmed to 2.

    Regards,
    Marc