u-boot Splash screen on dvo2

Hello, Craig Totel

I will gather some information about the dvo2 support, and I will let you know.

Thank you.

BR

Vladimir

Hello,

I am sorry, this information is not available. It is not possible to implement u-boot dvo2 splash screen. You could contact your local field engineer for more details.

BR

Vladimir

Craig,

We've enabled boot logo on DM814x for one customer. Please email me, @ renjith.thomas@pathpartnertech.com if you are looking for boot logo support in u-boot.

hi Renjith.......

its suhas.m  again...... im reminding u that im using DM3730 on Linux PSP 04.02.00.07..... kernel version 2.6.37.....even we r in need of getting splash screen @ u-boot stage.. can u pls provide a patch or similar changes......

thnx in advance renjith... :)

Suhas,

Did you check the current u-boot for the LCD boot logo support? I don't have a patch for DM3730 boot logo available with me. It needs to be developed, if its not available. 

my u-boot version is u-boot-2010.06-psp04.02.00.07.sdk  

We have added to the existing U-Boot logo patches to enable DVO2 output simultaneously.  It only requires a few changes to the existing code.  I believe the VPSS register descriptions and offsets are protected by NDA, so I believe I would need TI's permission to share the few changes I made to allow DVO2 output.

Hey Nick,

What processor are you using?  We are using the DaVinci TMS320DM816x.  The TI employee (Vladimir ) post above, claims that it is not possible.  

We do have a NDA with TI.  It just has been a painful process to get the register information for the video core.  Hopefully we will have this soon!  So the changes to support dv02 are minor?

Thanks,

Craig 

We are using the DM8148.  There were only 4 changes necessary to enable DVO2, but I am unsure if they would easily translate to the DM8168.  Comparing ti814x_logo.c to ti816x_logo.c, it seems like it might.  The 814x code appears to be more heavily commented, and does a lot of the same things, so you may be able to find some guidance there.

dispmgr_setup_layers needs to write to the DVO2 register, not just VPS_COMP_HDMI_VOUT1

ti816x_vps_init needs to set additional bits in VPS_COMP_STATUS

The huge block of code in ti816x_configure_hdvenc720P60 seems to be configuring the HDMI venc.  That will need to be done for the DVO2 Venc.

On the TI8148, VIDEO_PLL_CLKSRC needs to be configured to use VIDEO_PLL_CLK2 for the hd_venc_g_clk.  Not sure how that translates or if its necessary.

Hello,

HDVPSS internal document is not available even under NDA.

Thank you.

BR

Vladimir

 Hello Nick:

            For Adding Dvo2 support for DM8148,you say only have 4 changes need to add,Now I am using DM8148,can you help me how to add the 4 changes for adding DVO2?

                 Thanks very much .

The changes I made to add DVO2 support.  Some of this might not be necessary, but it seems to work okay.  Code I added is in blue text.

In drivers/video/firmware.c : dispmgr_setup_layers

__raw_writel(layer_ctrl, VPS_COMP_HDMI_VOUT1);
__raw_writel(layer_ctrl, VPS_COMP_HDMI_VOUT0);
__raw_writel(layer_ctrl, VPS_COMP_DVO2);

In drivers/video/ti814x_logo.c : ti814x_pll_config_hdvpss

u32 rd_osc_src;
rd_osc_src = __raw_readl(PLL_VIDEO2_PINMUX);
rd_osc_src &= 0xFFFFFFFE;
rd_osc_src |= (1<<24); /* vout0 clock source the same as hdmi source i.e HDMI PHY*/
__raw_writel(rd_osc_src, PLL_VIDEO2_PINMUX);
ti814x_pll_configure(PLL_HDVPSS_BASE, 19, 800, 4, 0x00000801);
}

In drivers/video/ti814x_logo.c : ti814x_vps_init

/* enable all video encoders */
__raw_writel(0xD, VPS_CLKC_VENC_ENABLE);
/* enable comp units */
__raw_writel(0 | (1 << 0), VPS_COMP_STATUS); // HDMI enable
/* enable comp units HDMI/HDCOMP/DVO2 */
__raw_writel(0 | (1 << 0) | (1 << 8) | (1 << 16), VPS_COMP_STATUS);
/* set background color */
__raw_writel(LOGO_BGCOLOR, VPS_COMP_BGCOLOR);

In drivers/video/ti814x_logo.c : ti814x_pll_config_hdmi

rd_osc_src &= 0xFFFFFFFE;
rd_osc_src |= (1<<24); /* vout0 clock source the same as hdmi source i.e HDMI PHY*/
__raw_writel(rd_osc_src, PLL_VIDEO2_PINMUX);

In drivers/video/ti814x_logo.c : ti814x_set_mode (This example is for a custom XGA timing, but you can use your desired res)

//configure dvo2
 ti814x_vps_configure_venc(VPS_REG_BASE + 0xA000, 1024, 1104, 1240, 1265,
768, 768, 774, 856, 0, 1, 1);
//configure hdmi
ti814x_vps_configure_venc(VPS_REG_BASE + 0x6000, 1024, 1104, 1240, 1265,
768, 768, 774, 856, 0, 1, 1);

In include/logo.h

#define VPS_COMP_HDMI_VOUT1 (VPS_REG_BASE + 0x5204)
#define VPS_COMP_HDMI_VOUT0 (VPS_REG_BASE + 0x5208)
#define VPS_COMP_DVO2 (VPS_REG_BASE + 0x520C)

 Hello  Nick Reed:

                    Thanks very much for you replying ,according to your advice,I have changed my u-boot——(u-boot-2010.06-psp04.04.00.01/ezsdk_5_05_01_04_dm814x)，

And I use the MISTRAL EVM8148 board,the LCD parameter was like this in the PSP packages:/etc/init.d/loadfireware.sh

                     echo 33500,800/164/89/10,480/10/23/10,1 > /sys/devices/platform/vpss/display1/timings

so ,in ti814x_set_mode,I configure like this:

                   ti814x_vps_configure_venc(VPS_REG_BASE + 0xA000, 800, 964, 1053, 1063,
                                            480, 490, 513, 523, 0, 1, 1);

But I still can't see  anything on the LCD,and I can see the logo bmp on hdmi(comareing with  without changing anything,the hdmi showsin the flickering ).So, any other I need to do  if I want see the logo bmp on LCD at the uboot stage?

         I'm looking forward to your  advice .Thanks very much.

         Best Regards！

                                                                                                                                   zhichao.

Is the backlight turned on?  If not, you'll have to dig through the kernel to find the steps necessary to turn on the backlight.

I'm using a digital display connected to a custom board, so we have a different backlight chip and steps necessary to turn it on.

Hello Nick Reed:

                           Very appreciate your advice,according to your suggestion,I turn on the backlight of LCD,and I can see something(but can't  see the logo bmp clearly) on the LCD now,and  the screen is glittering until the logotime is on,and when I change the following parameter:
                            ti814x_vps_configure_venc(VPS_REG_BASE + 0xA000, 800, 964, 1053, 1063,480, 490, 513, 523, 0, 1, 1);

    I can see the effect on the lcd screen ,so the DVO2 now  maybe work normally, But why I can't see the logo bmp clearly?and why the lcd screen is still flickering?

    I doubt the parameter of My LCD was not configured  correctly,What is more,My linux kernel Lcd driver was ok  if  using the following parameter:

                       echo 51200,1024/200/100/20,600/10/15/10,1 > /sys/devices/platform/vps s/display1/timings

 So：

1、how can I use the above parameter to configure the ti814x_vps_configure_venc(VPS_REG_BASE + 0xA000,-------------------)        

2、except configureing  ti814x_vps_configure_venc correctly,any other reasons may be result the flicker of the LCD?

           Best Regards

                                                                                                                     zhichao.

I believe for that resolution you'll need to configure the PLLs differently, as you have a different pixel/clock rate.  We are using custom timings for our display, as the official ones didn't seem to flicker and take a little while to settle in from U-Boot.  There's a chance you may need to do the same thing and tweak the parameters slightly.

In ti814x_set_mode, you probably need something like this for your resolution, and will need to define CONFIG_MY_RESOLUTION somewhere:

static int ti814x_set_mode(int dispno,int xres, int yres)
{
#ifdef CONFIG_480P
/*modeline "720x480" 27.000 720 736 798 858 480 489 495 525 -hsync -vsync*/
if (ti814x_pll_config_hdmi(27000000) == -1)
return -1;
ti814x_hdmi_enable(27000000);
ti814x_vps_configure_venc(VPS_REG_BASE + 0x6000, 720, 736, 798, 858,
480, 489, 495, 525, 0, 1, 1);
#elif defined (CONFIG_MY_RESOLUTION)
if (ti814x_pll_config_hdmi(51200000) == -1)
return -1;
ti814x_hdmi_enable(51200000);
//configure dvo2
ti814x_vps_configure_venc(VPS_REG_BASE + 0xA000, 1024, 1224, 1324, 1344, 600, 610, 625, 635, 0, 1, 1);
//configure hdmi
ti814x_vps_configure_venc(VPS_REG_BASE + 0x6000, 1024, 1224, 1324, 1344, 600, 610, 625, 635, 0, 1, 1);
#else
/* ModeLine "1920x1080" 148.50 1920 2008 2052 2200 1080 1084 1088 1125 +HSync +VSync */
if (ti814x_pll_config_hdmi(148500000) == -1)
return -1;
ti814x_hdmi_enable(148500000);
ti814x_vps_configure_venc(VPS_REG_BASE + 0x6000, 1920, 2008, 2052,
2200, 1080, 1084, 1088, 1125, 0, 0, 0);
#endif
ti814x_pll_hdmi_setwrapper_clk();

return 0;
}

And... looking into the code it looks like there's a good chance that 51.2 mhz clock isn't handled properly by ti814x_pll_get_dividers.  You can see it supports 5 frequencies at the moment.  You'll have to add your own case for handling the 51200000, and set the values properly.  The easiest way to figure out the correct values may be to track down the registers for the DVO2 PLL, configure things in Linux properly, then use devmem2 to dump the values of those registers.

Hi,

You can look into frame start event as well since incorrect setting in this field can also cause flicker in the output..

Regards,

Brijesh Jadav

Hello Brijesh Jadav and Nick Reed:

  How can configure the  frame start event ?Now,My linux kernel Lcd driver was ok  if  using the following parameter:

           echo 51200,1024/200/100/20,600/10/15/10,1 > /sys/devices/platform/vps s/display1/timings

So,I use the following settings in uboot:

     1、  ti814x_vps_configure_venc(VPS_REG_BASE + 0xA000, 1024, 1024+200+100, 1024+200+100+20, 1344, 600, 625, 635, 635, 0, 1, 1);

     2、 and,I configure the LCD clock:

                    if (ti814x_pll_config_hdmi(51200000) == -1)
                   {
                           return -1;
                    }
               ti814x_hdmi_enable(51200000);

  3、What's more,for 51.2M to my lcd clock,I add the followings ：

static int ti814x_pll_get_dividers(u32 req_out_clk, int hdmi,
      struct pll_config_t* config)
{

-----------------------     

nt32_t ret = -1;
 float ref_clk, dco_clk, clk_out;
 float best_delta;

 config->n = 0;
 config->m = 0;
 config->m2 = 0;
 config->clk_ctrl = 0;
 best_delta = 1E20;
 if(hdmi) {
  config->n = 19;
  config->m = 1485;
  config->m2 = 10;
  config->clk_ctrl = 0x200a1001;
         if(req_out_clk == 74250000) {
                 config->n = 19;
   config->m = 742;
   config->m2 = 10;
   config->clk_ctrl = 0x20020801;
  }

       else if(req_out_clk==51200000)
         {
                 printf("Config IPtv clock 51.2Mhz\n");
                 config->n = 19;
                 config->m = 512;
                 config->m2 = 10;
                 config->clk_ctrl = 0x20020801;
         }

}

  But,still flicked,and can not see anything,except  the dotted lines are still flickering.

 Last,In the kernel,when the LCD work ok,I read the followings registers int the linux-kernel/drivers/video/ti81xx/ti81xxfb/ti81xxfb_ioctl.c

 -----------------------------------------------------------

#define PLL_REG_BASE            0x481C5000
#define PLL_VIDEO2_PWRCTRL            (PLL_REG_BASE + 0x0200)
#define PLL_VIDEO2_CLKCTRL            (PLL_REG_BASE + 0x0204)
#define PLL_VIDEO2_TENABLE            (PLL_REG_BASE + 0x0208)
#define PLL_VIDEO2_TENABLEDIV         (PLL_REG_BASE + 0x020C)
#define PLL_VIDEO2_M2NDIV             (PLL_REG_BASE + 0x0210)
#define PLL_VIDEO2_MN2DIV            (PLL_REG_BASE + 0x0214)
#define PLL_VIDEO2_FRACDIV            (PLL_REG_BASE + 0x0218)
#define PLL_VIDEO2_BWCTRL             (PLL_REG_BASE + 0x021C)
#define PLL_VIDEO2_FRACCTRL           (PLL_REG_BASE + 0x0220)
#define PLL_VIDEO2_STATUS             (PLL_REG_BASE + 0x0224)
#define PLL_VIDEO2_PINMUX             (PLL_REG_BASE + 0x02C8)
#define PLL_OSC_SRC_CTRL              (PLL_REG_BASE + 0x02C0)

#define PLL_HDVPSS_BASE               PLL_HDVPSS_PWRCTRL
#define PLL_VIDEO2_BASE               PLL_VIDEO2_PWRCTRL
#define PLL_HDVPSS_PWRCTRL            (PLL_REG_BASE + 0x0170)

#define VPS_REG_BASE                    0x48100000+0xA000

          unsigned int  val= omap_readl(PLL_REG_BASE);
          printk(KERN_INFO "PLL_REG_BASE value is %x\n",val);

          val= omap_readl(PLL_VIDEO2_CLKCTRL);
          printk(KERN_INFO "PLL_VIDEO2_CLKCTRL value is %x\n",val);

          val= omap_readl(PLL_VIDEO2_STATUS);
          printk(KERN_INFO "PLL_VIDEO2_STATUS value is %x\n",val);

          val= omap_readl(PLL_OSC_SRC_CTRL);
          printk(KERN_INFO "PLL_OSC_SRC_CTRL value is %x\n",val);

          //--------parameter--------
          val= omap_readl(VPS_REG_BASE);
          printk(KERN_INFO "VPS_REG_BASE value is %x\n",val);

          printk(KERN_INFO " 0x28 value is %x\n",omap_readl(VPS_REG_BASE+0x28));
          printk(KERN_INFO " 0x30 value is %x\n",omap_readl(VPS_REG_BASE+0x30));
          printk(KERN_INFO " 0x3c value is %x\n",omap_readl(VPS_REG_BASE+0x3c));
          printk(KERN_INFO " 0x40 value is %x\n",omap_readl(VPS_REG_BASE+0x40));
          printk(KERN_INFO " 0x44 value is %x\n",omap_readl(VPS_REG_BASE+0x44));
          printk(KERN_INFO " 0x48 value is %x\n",omap_readl(VPS_REG_BASE+0x48));
          printk(KERN_INFO " 0x54 value is %x\n",omap_readl(VPS_REG_BASE+0x54));
          printk(KERN_INFO " 0x58 value is %x\n",omap_readl(VPS_REG_BASE+0x58));
          printk(KERN_INFO " 0x5c value is %x\n",omap_readl(VPS_REG_BASE+0x5c));
          printk(KERN_INFO " 0x64 value is %x\n",omap_readl(VPS_REG_BASE+0x64));

So,I use the above values to add the following registers int uboot:

1、

static void ti814x_vps_configure_venc(u32 cfg_reg_base, int hdisp, int hsyncstart,
int hsyncend, int htotal, int vdisp, int vsyncstart, int vsyncend, int vtotal,
    int enable_invert, int hs_invert, int vs_invert)
{

//mask all before code

//add the value I read from the kernel

__raw_writel(VPS_REG_BASE+0xA000+0x28,0x8427b540);--------------------------------------1
 __raw_writel(VPS_REG_BASE+0xA000+0x30,0x14408075);-------------------------------------2
 __raw_writel(VPS_REG_BASE+0xA000+0x3c,0x14400078);
  __raw_writel(VPS_REG_BASE+0xA000+0x40,0x22000);
 __raw_writel(VPS_REG_BASE+0xA000+0x44,0x258000);
  __raw_writel(VPS_REG_BASE+0xA000+0x48,0xa009000);
  __raw_writel(VPS_REG_BASE+0xA000+0x54,0x14400070);
 __raw_writel(VPS_REG_BASE+0xA000+0x58,0x22001);
  __raw_writel(VPS_REG_BASE+0xA000+0x5c,0x259172);
 __raw_writel(VPS_REG_BASE+0xA000+0x64,0xa00413d);

  __raw_writel((enable_invert << 25)
 | (hs_invert << 24)
 | (vs_invert << 23)
 | (3 << 16) /* video out format: 10 bit, separate syncs */
 | (1 << 13) /* bypass gamma correction */
 | (1 << 5)  /* bypass gamma correction */
 | (1 << 4)  /* bypass 2x upscale */
 | (1 << 0) /* 480p format */
 , cfg_reg_base);
 __raw_writel(__raw_readl(cfg_reg_base) | 0x40000000, cfg_reg_base + 0x00); /* start encoder *

}

But,the uboot will stop at "2",and  can not go on running.

2、Configure CLKCTRL

static void ti814x_pll_configure(u32 baseAddr, u32 n, u32 m, u32 m2,
             u32 clkCtrlValue)

{

static void ti814x_pll_configure(u32 baseAddr, u32 n, u32 m, u32 m2,
             u32 clkCtrlValue)
{
 u32 m2nval, mn2val, clkctrl, clk_out, ref_clk, clkout_dco = 0;
 u32 status;

 m2nval = (m2 << 16) | n;
 mn2val =  m;
 ref_clk     = OSC_FREQ / (n+1);
 clkout_dco  = ref_clk * m;
 clk_out     = clkout_dco / m2;
 __raw_writel(m2nval, (baseAddr + M2NDIV));
 __raw_writel(mn2val, (baseAddr + MN2DIV));
 __raw_writel(0x1, (baseAddr + TENABLEDIV));
 __raw_writel(0x0, (baseAddr + TENABLEDIV));
 __raw_writel(0x1, (baseAddr + TENABLE));
 __raw_writel(0x0, (baseAddr + TENABLE));
 clkctrl = __raw_readl(baseAddr + CLKCTRL);
 clkctrl = (clkctrl & ~(7 << 10 | 1 << 23)) | clkCtrlValue;
 __raw_writel(clkctrl, baseAddr + CLKCTRL);

 //IPTV_DEBUG
 __raw_writel(0x28131011, baseAddr + CLKCTRL);*/

 do {
  status = __raw_readl(baseAddr + STATUS);
 }
 while ((status & 0x00000600) != 0x00000600);
}

}

 Thanks very much.

Hi,

Could you tell me which graphics plane you are using? register address is different for different grpx plane.

Regards,

Brijesh Jadav

Hello Brijesh Jadav :

  How can I know  which graphics plane I am using?In kernel,I use the followings settings and work ok,so I may be use the graphics0.right?

     echo 1:dvo2 > /sys/devices/platform/vpss/graphics0/nodes
     echo 0 > /sys/devices/platform/vpss/display1/enabled

     echo 51200,1024/200/100/20,600/10/15/10,1 > /sys/devices/platform/vpss/display1/timings
     echo triplediscrete,rgb888 > /sys/devices/platform/vpss/display1/output
     echo 1 > /sys/devices/platform/vpss/display1/enabled

And,the before,I use the __raw_writel(VPS_REG_BASE+0xA000+0x64,0xa00413d) I found was wrong,the value and the register addr should be change place,But only still only can see dotted lines are flickering.

                           Thanks.

Hi,

Can you share the code of the api dispmgr_setup_layers?

Regards,

Brijesh Jadav

Hello Brijesh Jadav:

The  dispmgr_setup_layers is listed,the red parts was added by me:

static u32 dispmgr_setup_layers(u32* desc_buffer, int stride,int width, int height,
              u32 paddr)
{
 u32 size = 0;
 u32* desc;
 int chan;
 int x = 0;
 int y = 0;
 int i, time = 0 , num_desc=0;
 char *s;
 u32 layer_ctrl;
 
 desc = desc_buffer ;
 layer_ctrl = 0x0000E400;

 /*
  * set up data descriptors for GRPX units
  */
   
#ifdef CONFIG_GRPX0
 layer_ctrl |= 1 << (2);  /* enable GRPXx layer */
#elif defined CONFIG_GRPX1
 layer_ctrl |= 1 << (1);  /* enable GRPXx layer */
#else
 layer_ctrl |= 1 << (0);  /* enable GRPXx layer */
#endif

#ifdef CONFIG_GRPX0
 chan = GRPX0_CHANNEL_NUMBER;
#elif defined CONFIG_GRPX1
 chan = GRPX1_CHANNEL_NUMBER;
#else
 chan = GRPX2_CHANNEL_NUMBER;
#endif

 if ((s = getenv("logotime")) != NULL) {
  time = simple_strtol(s, NULL, 10);
  
      if(time > MAX_LOGO_TIME) {
   printf("Value of logotime is large, setting to default value\n");
   time = DEFAULT_LOGO_TIME;
  }
 }
 else {
  time = DEFAULT_LOGO_TIME;
 }

 num_desc = time * LOGO_TIME_MULTIPLIER;
 
 /* set up data transfer descriptor */
 for(i = 0; i < num_desc; i++) {
      desc[0] = 0
   | (DATA_TYPE << 26) /* RGB-888 */
   | (0 << 25)  /* no notification */
   | (0 << 24)  /* field number */
   | (0 << 23)  /* 2-dimensional data */
   | (0 << 20)  /* +1 line skip (even) */
   | (0 << 16)               /* +1 line skip (odd) */
   | (stride);  /* line stride */
  desc[1] = 0
   | (width << 16)  /* line length in pixels */
   | (height);  /* number of rows*/
  desc[2] = paddr;
  desc[3] = 0
       | (0xA << 27)  /* packet type */
   | (0 << 26)  /* 1D mode */
   | (0 << 25)  /* inbound direction */
   | (chan << 16)  /* channel */
   | (0 << 9)  /* priority */
   | (chan << 0);  /* next channel */
  desc[4] = 0
   | (width << 16)  /* region width */
   | (height);   /* region height */
  desc[5] = 0
   | (x << 16)  /* horizontal start */
   | (y << 0);  /* vertical start */
  desc[6] = 0
   | (1 << 7)  /* first region */
   | (1 << 8);  /* last region */
  desc[7] = 0;
  desc += 8;
  size += 32;
 }
 __raw_writel(layer_ctrl, VPS_COMP_HDMI_VOUT1);

#ifdef UBOOT_DVO2
 __raw_writel(layer_ctrl, VPS_COMP_HDMI_VOUT0);
 __raw_writel(layer_ctrl, VPS_COMP_DVO2);
#endif

 return size;
}

Hi,

Can you check which one of the below macro is defined?

#ifdef CONFIG_GRPX0
 layer_ctrl |= 1 << (2);  /* enable GRPXx layer */
#elif defined CONFIG_GRPX1
 layer_ctrl |= 1 << (1);  /* enable GRPXx layer */
#else
 layer_ctrl |= 1 << (0);  /* enable GRPXx layer */
#endif

Regards,

Brijesh Jadav

Hello Brijesh Jadav:

         I have check that I use the CONFIG_GRPX2 now(not define CONFIG_GRPX0 and CONFIG_GRPX1),if I define CONFIG_GRPX0 or CONFIG_GRPX1,I found there is nothing on the LCD,and only white screen.Thanks.

Hi,

Could you please check if the macro VPDMA_GRPX2_DATA_CSTAT is defined and if it is, can you add below line?

vpdma_write32(VPDMA_GRPX2_DATA_CSTAT,0x00000400);

Regards,

Brijesh Jadav

Hi Brijesh Jadav:

1、 There is no  vpdma_write32 fun in the uboot,and there have the follwing infor in the firmware.c:

#ifdef CONFIG_GRPX0
 __raw_writel(0x00001C00, VPDMA_GRPX0_DATA_CSTAT);
#elif defined CONFIG_GRPX1
 __raw_writel(0x00001C00, VPDMA_GRPX1_DATA_CSTAT);
#else
 __raw_writel(0x00001C00, VPDMA_GRPX2_DATA_CSTAT);
#endif

according to your advice ,may be I use :

 __raw_writel(0x00000400, VPDMA_GRPX2_DATA_CSTAT);this will OK?

2、And may I ask you another question?

     How to configure gpio in the U-boot？

      eg:I want to enbale the ninth pin in the bank 3,and set the pin as output,and output value 1.

     But the U-boot will stop when I use the followings operation:(if I use only the __raw_writel,and the uboot will stop here,eg:  __raw_writel(l,0x481AE134))

 u32 l; 

 l  = __raw_readl(0x481AE13C);

 l |= 1 << 9;

/*

0x481AE13C: The GPIO_DATAOUT register is used for setting the value of the GPIO output pins. Data is written to the
GPIO_DATAOUT register synchronously with the interface clock. This register can be accessed with
direct read/write operations or using the alternate ‘Set/Clear’ feature. This feature enables to set or clear
specific bits of this register with a single write access to the set data output register
(GPIO_SETDATAOUT) or to the clear data output register (GPIO_CLEARDATAOUT) address.

*/
 __raw_writel(l,0x481AE134);//Enable output*/
 __raw_writel(l,0x481AE13C);//Set the out put value 1

/*

0x481AE194:Writing a 1 to a bit in the GPIO_SETDATAOUT register sets to 1 the corresponding bit in the
GPIO_DATAOUT register; writing a 0 has no effect. A read of the GPIO_SETDATAOUT register returns
the value of the data output register (GPIO_DATAOUT).

*/

__raw_writel(l,0x481AE194);

 So,I want to know why I can't use the _raw_writel fun ,and if there is some problem about my register addr?

Thanks very much.

Hello  Brijesh Jadav:

   I capture the result photo(I show the  penguin default ) ,as the followings:

1、if  I use

__raw_writel(0x00001C00, VPDMA_GRPX2_DATA_CSTAT);

then the photo is the following,and the picture is still flickering.

2、if i use:

Hi,

__raw_writel(0x00000400, VPDMA_GRPX2_DATA_CSTAT); is correct statemenet to configure frame start event.

I am not sure about GPIO.

Regards,

Brijesh Jadav

Hi,

Venc configuration parameters look ok. I am not sure whether below PLL parameters are correct or not. Please TRM to find out how to calculate correct parameters for the given pclk.

config->n = 19;
                 config->m = 512;
                 config->m2 = 10;
                 config->clk_ctrl = 0x20020801;

Regards,

Brijesh Jadav

Hello Brijesh Jadav:

Then How can I configure clock if I use 51.2Mhz?According to the code,I found there may be only two places need to modify:

1、

ti814x_pll_config_hdmi(27000000) ;

In this function,will call the function ti814x_pll_get_dividers

------------------------------

static int ti814x_pll_config_hdmi(u32 freq)
{

 if (ti814x_pll_get_dividers(freq, 1, &config) == -1)
  return -1;
 ti814x_pll_configure(PLL_VIDEO2_BASE, config.n, config.m, config.m2,
             config.clk_ctrl);

------------

}

how to fix on the m . m2  config->.clk_ctrl value?

                config->n = 19;
                 config->m = 512;
                 config->m2 = 10;
                 config->clk_ctrl = 0x20020801;

Hi,

this is correct place, what i wanted you to check is whether the values of n, m, and m2 are correct for the pclk you require. it might not be supporting the pclk that you require for your lcd, so you will need to get the correct parameters and add it over here in this part of the code.

Regards,

Brijesh Jadav

hello Brijesh Jadav：

  Now,may be there is some  problems about the values of n, m, and m2 ,but how to  calculate them?Can you help me,My LCD clock is 51.2M.Thanks a lot.

Hi everyone      

We are working on DM8148 and tried to enable SD/Composite to display logo at start up. 

And we know the u-boot currently only supports a splash screen on HDMI.

We are using ti-ezsdk_dm814x-evm_5_04_00_11.

Have anyone is success working splash screen on SD/Composite ?

 if available please help us?

 Or kindly provide some suggestion?

just mask