DM8168 4Gb DDR

thank

         I mean  whether a different configuration  in the  MLO  file?  I have used the 4 chips (2Gb x16 ) , 8 chips (2Gb x8) on our earlier board and  worked well.

         but this time the 4Gb device can't boot ,so i want to know whether  i must  set  a different configuration ?  

Can you explain more. Do you mean you have a single 4Gbx16 memory chip to one EMIF interface and the other EMIF is not populated ? Are you using the DVR RDK uboot without any modifications ? Which RDK release are you using

I use 4 chips (4Gb devices,16 data bits )for the two EMIFS,and the RDK version is 3.0

i want to know whether the MLO file need a special configuration?

I have designed many boards,using 2Gb devices(x16 or x8), and worked very well,but the 4Gb board can not boot up using the MLO and uboot.

Hello,

4 chips (4Gb each, 16x) means that you will have 2GB address space in total, is that correct?

Check this thread: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/156047/570696.aspx#570696

The below info is valid for EZSDK, but may be the same is valid for RDK (I have no access to RDK, so I can not be sure):

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map

In the default uboot program ( in file $(EZSDK_ROOT)/board-support/u-boot-<REL-TAG>/board/<ti8168 or ti8148>/ti/evm.c), 2GB physical memory is mapped using register 3 and 4. Register 1 and 2 are unused.

• System Address 0x80000000 is mapped to physical address 0x00000000
• System Address 0xC0000000 is mapped to physical address 0x20000000

Following code programs the LISA registers for 2GB physical memory (default configuration).

/* Program the DMM to for 2 GB (interleaved) configuration */

__raw_writel(0x0, DMM_LISA_MAP__0); /* Register 0 is unused */

__raw_writel(0x0, DMM_LISA_MAP__1); /* Register 1 is unused */

__raw_writel(0x80640300, DMM_LISA_MAP__2); /* Register 2 maps 0x80000000 to 0x00000000, length 1GB */

__raw_writel(0xC0640320, DMM_LISA_MAP__3); /* Register 3 maps 0xC0000000 to 0x20000000, length 1GB */

I also suspect that you will have to modify the ldrmemcfg_ddrSize unsigned integer variable (from file memsegdef_default.c) like below

/*----------------------------- Memory Segment configuration -----------------*/
#include <ldr_memseg.h>

//uint32_t ldrmemcfg_ddrSize = LDR_DDR_SIZE_1G ;
uint32_t ldrmemcfg_ddrSize = LDR_DDR_SIZE_2G ;

Some info here also:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/222065/785724.aspx?Redirected=true

I hope this will help.

Regards,

Pavel

Thanks for your answer.

as you mentioned above, I have used 2GB  address space on our earlier board, using 8 chips 2Gb devices(x8). So the 2GB memory segment configuration was OK.
I mean the 4Gb  DDR devices(x16) was used for the first time,but the board can't boot.Is there any differences from the 2Gb device and the 4Gb device for the configuration ?

thank you

Pls check if this post helps: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/120664.aspx

Hi,han han

I met the same issue with you,when i power on the board ,there is not any infomation on USART port......... do you have a solution?

where is "uint32_t ldrmemcfg_ddrSize = LDR_DDR_SIZE_2G " ?      

Hi Pavel,

We are upgrading our DM8168 board, currently with 1 GB DDR3 @ 800 MHz (16-bit symmetrical 4 x 256 MB) to 2 GB (16-bit symmetrical 4 x 512 MB). New chip is very similar to old part from the same manufacturer, essentially the major difference is adding another address line (A14).

Regarding LISA interleaving, the reference manual describes a scenario which looks like what we need (section 4.3.4.1.1 "Two Memory Controllers, 2GB DDR Symmetrical Distribution"). But those parameters don't look as what you suggested. Are they tested by someone?

Also, if it says "Section 1, Section 2 and Section 3 - identical to Section 0", do I still use only LISA_MAP registers 2 and 3, or do I configure all four of them?

I don't have the new hardware because it's still not in production, but I need to have the proper software on the day the hardware gets produced.

Thanks!

Hi Ivan,

Ivan Todorovic said:

Also, if it says "Section 1, Section 2 and Section 3 - identical to Section 0", do I still use only LISA_MAP registers 2 and 3, or do I configure all four of them?

Both options should work.

Thanks Renjith.

(Sorry for not being able to click "verify answer" since I didn't start this thread)

After some more reading and comparing the code with the DVR RDK U-Boot, I believe the default setting (which is the same as quoted by Pavel, and essentialy the same as in DVR RDK) will work fine with 2GB DDR3.

Thanks!