DM816x VOUT and VIN timing margin queries

•  From the datasheet we see that for video input signals the setup time margin is 3.75ns(min). This is mentioned in Page 264 of the datasheet. We see that when we take this value for 1080p video input this setup time margin comes around to be more than the half width of the clock period. We also compared this with the DM6467 setup time and DM6467 has a lower margin of 1.98ns(min). Can you please confirm whether this value is correct? If not, can you please share with us the proper values.

Datasheet is correct. These are MAX values, guaranteed by design and characterization across temp, voltage and process. DM6467 is a completely different processor in a completely different process technology etc… The increased uncertainty is due to the significantly higher number of mux options for the IO signals. It is true that timing is tight at the highest clock frequencies.

• Also it is mentioned in the Errata that for video out positive edge clocking is not supported (Advisory 2.1.47). And VOUT transitions will happen only on the negative edge of the clock. So the workaround mentioned here is to capture at the positive edge of the clock at the receiver. In the datasheet it has been mentioned that output delay time for VOUT can be between 1.64ns to 4.85ns.  Now if we consider the VOUT to be configured to 1080p60 video at 148.5MHz. The clock period will be 6.74ns. Now if we assume maximum delay of 4.85 ns then the data will not be valid at the next positive edge as this delay is more than half clock period value of 3.37ns. Our receiver always capture at the positive edge of the clock and has setup time margin of 1.3ns. Can you confirm from your side whether these values are proper as mentioned in the datasheet?

Datasheet is correct. These are MAX values, guaranteed by design and characterization across temp, voltage and process. The errata is really just trying to stress that the data actually changes on the falling edge and not the rising edge. It is still necessary to do a full timing analysis to make sure margins are in the correct place. The original datasheet incorrectly stated output transitions on the rising edge and gave timings with respect to that edge, but with adjusted numbers corresponding to a specific and max pixel clock frequency. This is obviously a broken methodology since it made it very difficult to calculate margins for other frequencies. For VOut clock to data it is the spread of max and min which is critical since this tells you where the window of uncertainty is, i.e. where you cannot capture data. In this case there is an uncertainty window of 3.21ns (4.85 – 1.64) that starts 1.64ns after the clock edge.

• Also going by the values given for VOUT and VIN we calculated that at 1080p60 if we do a loopback of video ports it wont work. This is because the VOUT port will give out at negative edge of the clock with a delay of min 1.64ns to max 4.85ns. At the VIN if we capture at positive edge then the setup time required is minimum of 3.75ns which will not meet in this case. Also if we capture at negative edge in that case also for 4.85ns delay again setup time will fail. However we have seen in our other boards that video loop through in Netra is working properly at 1080p60. Please comment on the same.