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TVP5158 BT.656 output timing can not match DM8168

Omin Chou
Genius 3555 points
Other Parts Discussed in Thread: TVP5158

Dear all,

DM8168 datasheet said the input setup time, data valid to VIN[X]A_CLK high had to be min 3.75ns as below.

So, I measured tvp5158 bt656 output timing. Unfortunately, the result is 2.5ns under the min spec 3.75ns.

Can anyone give me some hints to adjust tvp5158 registers or use hardware side to fill a vacancy on this portion? Thanks in advance.

B.R.

OC

  • 0
    TI__Mastermind 43875 points

    You should be able to use the TVP5158 output clock polarity to effectively move the clock edge a half cycle (TVP5158 register B2h bit 4).

    Can you show the timing diagram showing the relationships for your measurement points 'position 1' thru 'position 7' and let me know what frequency you are running the video outputs at.

    There should be clock to a half cycle of setup available since the TVP outputs change close to the falling edge of the clock. Even at 108MHz (period = 9.2ns) then 1/2 cycle time is 4.6ns and max clock to data is 1.5ns which would give a setup time of 3.1ns and not 2.5ns. (granted there are propagation delays but these should be matched for both clock and data, and and delta should be small).

    Where did the 'Spec.' number of min = 3.75ns come from? The TVP5158 has a min clock to data time of 1.5ns for 108MHz and 4.86ns for 27MHz.

    Inverting the clock should meet all timing requirements since the TVP5158 has a positive output delay time and the DM has a zero input hold time requirement.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 30 points

    Hi Steve

    We try to adjust TVP5158 register in timing was improved and it can meet the SPEC.

    But margin too small at hold time after regulating. Do you have any idea? or suggestion?



    BR,

    Zhiang


  • 0 in reply to Huang bo
    TI__Mastermind 43875 points

    First, I would comment that you do have margin, even though you feel it is small. This may not be a real issue since the DM input specified hold time is a max number (this can actually be negative in real life).

    If you are uncomfortable with this margin then you could invert the clock and then use trace length adjustments and/or active buffers to delay the clock slightly.

    Personally I would prefer to see the active clock edge much closer to the center of the eye diagram.

    BR,

    Steve