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Unhandled Exception in m3video

kisung cho
Expert 1460 points

Hi experts.

i'm using DVRRDK3.5 and use usecase VDEC_VDIS .

when i put encoded data to my NVR , i met error as follows.

we are using DDR3  4G-bit( x16 ) x4(part is K4B4G1646B-HCK0). we changed  EMIF , but we can't set swleveling because we don't have JTAG interface in the h/w.

does anyone show me  common DDR3_SW_LEVELING values of 4G-bit(x16) x4?

i think current DDR3_SW_LEVELING values adjusted DDR3 2G-bit(x8) x 8.

i want to know common sw leveling value of 4G-bit(x16) x4 .

any advice will be appreciated.

Best Regards. CHO

///////////////////// arch/arm/include/asm/arch-ti81xx/ddr_defs_ti816x.h /////////////////

/* For 796 MHz */
#if defined(CONFIG_TI816X_DDR3_796)
/*
#define EMIF_TIM1   0x1779C9FE
#define EMIF_TIM2   0x50608074
#define EMIF_TIM3   0x009F857F
#define EMIF_SDREF  0x10001841
#define EMIF_SDCFG  0x62A73832
#define EMIF_PHYCFG 0x00000110
*/
#define EMIF_TIM1   0x1779C9FE
#define EMIF_TIM2   0x50D87FF4
#define EMIF_TIM3   0x009F8CFF
#define EMIF_SDREF  0x10001844
#define EMIF_SDCFG  0x62A73832
#define EMIF_PHYCFG 0x00000110

1512.NHR_EMIF4_Register_Settings.xls

///////////////// ERROR LOG MESSAGE ////////////////////////////////

[m3video] Unhandled Exception:
 [m3video] Exception occurred in ThreadType_Task
 [m3video] handle: 0x31c02ff8.
 [m3video] stack base: 0x32636440.
 [m3video] stack size: 0x8000.
 [m3video] R0 = 0x32207e88  R8  = 0x3263e140
 [m3video] R1 = 0x323094a4  R9  = 0x91903a54
 [m3video] R2 = 0x00000000  R10 = 0x32200000
 [m3video] R3 = 0x00000140  R11 = 0x00000000
 [m3video] R4 = 0x32207e88  R12 = 0x0000bd63
 [m3video] R5 = 0x3263e140  SP(R13) = 0x3263e008
 [m3video] R6 = 0x32206684  LR(R14) = 0x917feea3
 [m3video] R7 = 0x00000000  PC(R15) = 0x91811280
 [m3video] PSR = 0x41000000
 [m3video] ICSR = 0x00400803
 [m3video] MMFSR = 0x00
 [m3video] BFSR = 0x00
 [m3video] UFSR = 0x0001
 [m3video] HFSR = 0x40000000
 [m3video] DFSR = 0x00000000
 [m3video] MMAR = 0xe000ed34
 [m3video] BFAR = 0xe000ed38
 [m3video] AFSR = 0x00000000
 [m3video] Terminating Execution...

  • 0
    TI__Guru 59700 points

    S/W leveling has to be done for your board. There are no common values that can be used. The uboot that is part of DVR RDK has the same slave ratio search algorithm that is implemented in CCS based s/w leveling .out file so you don't need CCS to do s/w leveling.You can program the correct values and uboot will print the DQS values.You should then recompile the uboot with the printed values.

  • 0 in reply to Badri Narayanan
    Expert 1460 points

    Hi , thanks for your reply.

    i don't understand your advice belows

    " You can program the correct values and uboot will print the DQS values."


    printed uboot result is the same at the ddr_defs_ti816x.h. How can i get the correct values ?

    could you advice more detail ?.

    Thanks .

    my u-boot log is as follows.

    U-Boot 2010.06 (Oct 17 2013 - 13:13:57)

    TI8168-GP rev 2.0

    HDVICP clk     : 600MHz
    L3 Fast clk    : 549MHz
    HDVPSS clk     : 274MHz
    Ducati M3 clk  : 274MHz
    DSP clk        : 1000MHz
    ARM clk        : 1200MHz
    DDR clk        : 796MHz

    ------------ PLL Settings --------------
    MAIN_N        : 56, MAIN_P: 1, OSC_FREQ: 27, FAPLL_K: 8

    MAIN_INTFREQ1 : 0xC, MAIN_FRACFREQ1: 0x189374, MAIN_MDIV1: 0x1
    MAIN_INTFREQ2 : 0xA, MAIN_FRACFREQ2: 0x147AE1, MAIN_MDIV2: 0x1
    MAIN_INTFREQ3 : 0xA, MAIN_FRACFREQ3: 0x147AE1, MAIN_MDIV3: 0x2
    MAIN_INTFREQ4 : 0xB, MAIN_FRACFREQ4: 0x0, MAIN_MDIV4: 0x2
    MAIN_INTFREQ5 : 0xC, MAIN_FRACFREQ5: 0x189374, MAIN_MDIV5: 0x8

    MAIN_MDIV6    : 0x3F
    MAIN_MDIV7    : 0x4


    --------- DDR PLL ----------
    DDR_N                  : 0x3B
    DDR_P                  : 0x1
    DDR_MDIV1              : 0x2
    DDR_INTFREQ2           : 0x8
    DDDDR_FRACFREQ2R_N     : 0xD99999
    DDR_MDIV2              : 0x1E
    DDR_INTFREQ3           : 0x8
    DDR_FRACFREQ3          : 0x0
    DDR_MDIV3              : 0x4
    DDR_INTFREQ4           : 0xE
    DDR_FRACFREQ4          : 0x0
    DDR_MDIV4              : 0x4
    DDR_INTFREQ5           : 0xE
    DDR_FRACFREQ5          : 0x0
    DDR_MDIV5              : 0x4

    ----------EMIF Timings (identical for 0 & 1)-------
    EMIF_TIM1   : 0x1779C9FE
    EMIF_TIM2   : 0x50D87FF4
    EMIF_TIM3   : 0x009F8CFF
    EMIF_SDREF  : 0x10001844
    EMIF_SDCFG  : 0x62A73832
    EMIF_PHYCFG : 0x00000110

    ----------SW LEVEL Info (EMIF 0) -------
    RD_DQS_GATE_BYTE_LANE0: 0x00000160
    RD_DQS_GATE_BYTE_LANE1: 0x00000178
    RD_DQS_GATE_BYTE_LANE2: 0x000001B3
    RD_DQS_GATE_BYTE_LANE3: 0x000001D6

    WR_DQS_RATIO_BYTE_LANE0: 0x0000007D
    WR_DQS_RATIO_BYTE_LANE1: 0x0000008F
    WR_DQS_RATIO_BYTE_LANE2: 0x000000A2
    WR_DQS_RATIO_BYTE_LANE3: 0x000000B2

    RD_DQS_RATIO_BYTE_LANE0: 0x00000037
    RD_DQS_RATIO_BYTE_LANE1: 0x00000037
    RD_DQS_RATIO_BYTE_LANE2: 0x00000038
    RD_DQS_RATIO_BYTE_LANE3: 0x0000003B

    WR_DATA_RATIO_BYTE_LANE0: 0x000000BD
    WR_DATA_RATIO_BYTE_LANE1: 0x000000CF
    WR_DATA_RATIO_BYTE_LANE2: 0x000000E2
    WR_DATA_RATIO_BYTE_LANE3: 0x000000F2

    ----------SW LEVEL Info (EMIF 1) -------
    RD_DQS_GATE_BYTE_LANE0: 0x0000015F
    RD_DQS_GATE_BYTE_LANE1: 0x00000171
    RD_DQS_GATE_BYTE_LANE2: 0x000001B5
    RD_DQS_GATE_BYTE_LANE3: 0x000001D3

    WR_DQS_RATIO_BYTE_LANE0: 0x0000006F
    WR_DQS_RATIO_BYTE_LANE1: 0x00000087
    WR_DQS_RATIO_BYTE_LANE2: 0x000000A5
    WR_DQS_RATIO_BYTE_LANE3: 0x000000B0

    RD_DQS_RATIO_BYTE_LANE0: 0x00000035
    RD_DQS_RATIO_BYTE_LANE1: 0x00000043
    RD_DQS_RATIO_BYTE_LANE2: 0x0000003F
    RD_DQS_RATIO_BYTE_LANE3: 0x00000038

    WR_DATA_RATIO_BYTE_LANE0: 0x000000AF
    WR_DATA_RATIO_BYTE_LANE1: 0x000000C7
    WR_DATA_RATIO_BYTE_LANE2: 0x000000E5
    WR_DATA_RATIO_BYTE_LANE3: 0x000000F0

  • 0 in reply to Badri Narayanan
    Prodigy 170 points

    Hi Badri


    we  want to use the uboot to instead CCS to detect the SW leveling parameters , the RDK version is 4.00.01, would u plz. tell us how to do with the Uboot ?